1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * QorIQ RDB boards configuration file
13 #include <linux/stringify.h>
15 #if defined(CONFIG_TARGET_P1020RDB_PC)
16 #define CONFIG_VSC7385_ENET
18 #define __SW_BOOT_MASK 0x03
19 #define __SW_BOOT_NOR 0x5c
20 #define __SW_BOOT_SPI 0x1c
21 #define __SW_BOOT_SD 0x9c
22 #define __SW_BOOT_NAND 0xec
23 #define __SW_BOOT_PCIE 0x6c
24 #define __SW_NOR_BANK_MASK 0xfd
25 #define __SW_NOR_BANK_UP 0x00
26 #define __SW_NOR_BANK_LO 0x02
27 #define CONFIG_SYS_L2_SIZE (256 << 10)
31 * P1020RDB-PD board has user selectable switches for evaluating different
32 * frequency and boot options for the P1020 device. The table that
33 * follow describe the available options. The front six binary number was in
34 * accordance with SW3[1:6].
35 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
36 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
37 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
38 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
39 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
40 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
41 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
43 #if defined(CONFIG_TARGET_P1020RDB_PD)
44 #define CONFIG_VSC7385_ENET
46 #define __SW_BOOT_MASK 0x03
47 #define __SW_BOOT_NOR 0x64
48 #define __SW_BOOT_SPI 0x34
49 #define __SW_BOOT_SD 0x24
50 #define __SW_BOOT_NAND 0x44
51 #define __SW_BOOT_PCIE 0x74
52 #define __SW_NOR_BANK_MASK 0xfd
53 #define __SW_NOR_BANK_UP 0x00
54 #define __SW_NOR_BANK_LO 0x02
55 #define CONFIG_SYS_L2_SIZE (256 << 10)
57 * Dynamic MTD Partition support with mtdparts
61 #if defined(CONFIG_TARGET_P2020RDB)
62 #define CONFIG_VSC7385_ENET
63 #define __SW_BOOT_MASK 0x03
64 #define __SW_BOOT_NOR 0xc8
65 #define __SW_BOOT_SPI 0x28
66 #define __SW_BOOT_SD 0x68
67 #define __SW_BOOT_SD2 0x18
68 #define __SW_BOOT_NAND 0xe8
69 #define __SW_BOOT_PCIE 0xa8
70 #define __SW_NOR_BANK_MASK 0xfd
71 #define __SW_NOR_BANK_UP 0x00
72 #define __SW_NOR_BANK_LO 0x02
73 #define CONFIG_SYS_L2_SIZE (512 << 10)
75 * Dynamic MTD Partition support with mtdparts
80 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
81 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
82 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
83 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
84 #elif defined(CONFIG_SPIFLASH)
85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
87 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
88 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
89 #elif defined(CONFIG_MTD_RAW_NAND)
90 #ifdef CONFIG_TPL_BUILD
91 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
92 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
93 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
94 #elif defined(CONFIG_SPL_BUILD)
95 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
96 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
97 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
98 #endif /* not CONFIG_TPL_BUILD */
101 #ifndef CONFIG_RESET_VECTOR_ADDRESS
102 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
105 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
106 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
108 #define CONFIG_HWCONFIG
110 * These can be toggled for performance analysis, otherwise use default.
112 #define CONFIG_L2_CACHE
114 #define CONFIG_SYS_CCSRBAR 0xffe00000
115 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
118 #define CONFIG_SYS_DDR_RAW_TIMING
119 #define CONFIG_SYS_SPD_BUS_NUM 1
120 #define SPD_EEPROM_ADDRESS 0x52
122 #if defined(CONFIG_TARGET_P1020RDB_PD)
123 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
125 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
127 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
128 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
129 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
131 /* Default settings for DDR3 */
132 #ifndef CONFIG_TARGET_P2020RDB
133 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
134 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
135 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
136 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
137 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
138 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
140 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
141 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
142 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
143 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
145 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
146 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
147 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
148 #define CONFIG_SYS_DDR_RCW_1 0x00000000
149 #define CONFIG_SYS_DDR_RCW_2 0x00000000
150 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
151 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
152 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
153 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
155 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
156 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
157 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
158 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
159 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
160 #define CONFIG_SYS_DDR_MODE_1 0x40461520
161 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
162 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
168 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
169 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
170 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
171 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
173 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
174 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
175 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
176 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
177 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
178 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
182 * Local Bus Definitions
184 #if defined(CONFIG_TARGET_P1020RDB_PD)
185 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
186 #define CONFIG_SYS_FLASH_BASE 0xec000000
188 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
189 #define CONFIG_SYS_FLASH_BASE 0xef000000
192 #ifdef CONFIG_PHYS_64BIT
193 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
195 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
198 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
201 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
203 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
204 #define CONFIG_SYS_FLASH_QUIET_TEST
205 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
207 #undef CONFIG_SYS_FLASH_CHECKSUM
208 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
209 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
211 #define CONFIG_SYS_FLASH_EMPTY_INFO
214 #ifdef CONFIG_NAND_FSL_ELBC
215 #define CONFIG_SYS_NAND_BASE 0xff800000
216 #ifdef CONFIG_PHYS_64BIT
217 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
219 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
222 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
223 #define CONFIG_SYS_MAX_NAND_DEVICE 1
225 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
226 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
227 | BR_PS_8 /* Port Size = 8 bit */ \
228 | BR_MS_FCM /* MSEL = FCM */ \
230 #if defined(CONFIG_TARGET_P1020RDB_PD)
231 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
232 | OR_FCM_PGS /* Large Page*/ \
240 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
248 #endif /* CONFIG_NAND_FSL_ELBC */
250 #define CONFIG_SYS_INIT_RAM_LOCK
251 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
252 #ifdef CONFIG_PHYS_64BIT
253 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
254 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
255 /* The assembler doesn't like typecast */
256 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
257 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
258 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
260 /* Initial L1 address */
261 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
262 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
263 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
265 /* Size of used area in RAM */
266 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
268 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
270 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
272 #define CONFIG_SYS_CPLD_BASE 0xffa00000
273 #ifdef CONFIG_PHYS_64BIT
274 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
276 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
278 /* CPLD config size: 1Mb */
281 #ifdef CONFIG_VSC7385_ENET
282 #define __VSCFW_ADDR "vscfw_addr=ef000000\0"
283 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
285 #ifdef CONFIG_PHYS_64BIT
286 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
288 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
291 #define CONFIG_SYS_VSC7385_BR_PRELIM \
292 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
293 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
294 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
295 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
297 /* The size of the VSC7385 firmware image */
298 #define CONFIG_VSC7385_IMAGE_SIZE 8192
302 #define __VSCFW_ADDR ""
306 * Config the L2 Cache as L2 SRAM
308 #if defined(CONFIG_SPL_BUILD)
309 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
310 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
311 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
312 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
313 #elif defined(CONFIG_MTD_RAW_NAND)
314 #ifdef CONFIG_TPL_BUILD
315 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
316 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
317 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
319 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
320 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
321 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
322 #endif /* CONFIG_TPL_BUILD */
326 /* Serial Port - controlled on board with jumper J8
330 #undef CONFIG_SERIAL_SOFTWARE_FIFO
331 #define CONFIG_SYS_NS16550_SERIAL
332 #define CONFIG_SYS_NS16550_REG_SIZE 1
333 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
334 #if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)
335 #define CONFIG_NS16550_MIN_FUNCTIONS
338 #define CONFIG_SYS_BAUDRATE_TABLE \
339 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
341 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
342 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
345 #if !CONFIG_IS_ENABLED(DM_I2C)
346 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
349 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
355 #define CONFIG_RTC_PT7C4338
356 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
357 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
359 /* enable read and write access to EEPROM */
361 #if defined(CONFIG_PCI)
364 * Memory space is mapped 1-1, but I/O space must start from 0.
367 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
368 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
369 #ifdef CONFIG_PHYS_64BIT
370 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
372 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
374 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
375 #ifdef CONFIG_PHYS_64BIT
376 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
378 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
381 /* controller 1, Slot 2, tgtid 1, Base address a000 */
382 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
383 #ifdef CONFIG_PHYS_64BIT
384 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
386 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
388 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
389 #ifdef CONFIG_PHYS_64BIT
390 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
392 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
395 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
396 #endif /* CONFIG_PCI */
398 #if defined(CONFIG_TSEC_ENET)
400 #define CONFIG_TSEC1_NAME "eTSEC1"
402 #define CONFIG_TSEC2_NAME "eTSEC2"
404 #define CONFIG_TSEC3_NAME "eTSEC3"
406 #define TSEC1_PHY_ADDR 2
407 #define TSEC2_PHY_ADDR 0
408 #define TSEC3_PHY_ADDR 1
410 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
411 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
412 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
414 #define TSEC1_PHYIDX 0
415 #define TSEC2_PHYIDX 0
416 #define TSEC3_PHYIDX 0
417 #endif /* CONFIG_TSEC_ENET */
422 #if defined(CONFIG_SDCARD)
423 #define CONFIG_FSL_FIXED_MMC_LOCATION
424 #elif defined(CONFIG_MTD_RAW_NAND)
425 #ifdef CONFIG_TPL_BUILD
426 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
428 #elif defined(CONFIG_SYS_RAMBOOT)
429 #define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
432 #define CONFIG_LOADS_ECHO /* echo on for serial download */
433 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
440 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
444 * Miscellaneous configurable options
448 * For booting Linux, the board info and command line data
449 * have to be in the first 64 MB of memory, since this is
450 * the maximum mapped by the Linux kernel during initialization.
452 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
453 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
456 * Environment Configuration
458 #define CONFIG_HOSTNAME "unknown"
459 #define CONFIG_ROOTPATH "/opt/nfsroot"
460 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
462 #include "p1_p2_bootsrc.h"
464 #define CONFIG_EXTRA_ENV_SETTINGS \
466 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
467 "loadaddr=1000000\0" \
468 "bootfile=uImage\0" \
469 "tftpflash=tftpboot $loadaddr $uboot; " \
470 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
471 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
472 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
473 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
474 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
475 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
476 "consoledev=ttyS0\0" \
477 "ramdiskaddr=2000000\0" \
478 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
479 "fdtaddr=1e00000\0" \
481 "jffs2nor=mtdblock3\0" \
482 "norbootaddr=ef080000\0" \
483 "norfdtaddr=ef040000\0" \
484 "jffs2nand=mtdblock9\0" \
485 "nandbootaddr=100000\0" \
486 "nandfdtaddr=80000\0" \
487 "ramdisk_size=120000\0" \
489 MAP_NOR_LO_CMD(map_lowernorbank) \
490 MAP_NOR_UP_CMD(map_uppernorbank) \
491 RST_NOR_CMD(norboot) \
492 RST_SPI_CMD(spiboot) \
494 RST_NAND_CMD(nandboot) \
495 RST_PCIE_CMD(pciboot) \
498 #define CONFIG_USB_FAT_BOOT \
499 "setenv bootargs root=/dev/ram rw " \
500 "console=$consoledev,$baudrate $othbootargs " \
501 "ramdisk_size=$ramdisk_size;" \
503 "fatload usb 0:2 $loadaddr $bootfile;" \
504 "fatload usb 0:2 $fdtaddr $fdtfile;" \
505 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
506 "bootm $loadaddr $ramdiskaddr $fdtaddr"
508 #define CONFIG_USB_EXT2_BOOT \
509 "setenv bootargs root=/dev/ram rw " \
510 "console=$consoledev,$baudrate $othbootargs " \
511 "ramdisk_size=$ramdisk_size;" \
513 "ext2load usb 0:4 $loadaddr $bootfile;" \
514 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
515 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
516 "bootm $loadaddr $ramdiskaddr $fdtaddr"
518 #define CONFIG_NORBOOT \
519 "setenv bootargs root=/dev/$jffs2nor rw " \
520 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
521 "bootm $norbootaddr - $norfdtaddr"
523 #endif /* __CONFIG_H */