2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * QorIQ RDB boards configuration file
14 #define CONFIG_PHYS_64BIT
17 #if defined(CONFIG_P1020MBG)
18 #define CONFIG_BOARDNAME "P1020MBG-PC"
20 #define CONFIG_VSC7385_ENET
22 #define __SW_BOOT_MASK 0x03
23 #define __SW_BOOT_NOR 0xe4
24 #define __SW_BOOT_SD 0x54
25 #define CONFIG_SYS_L2_SIZE (256 << 10)
28 #if defined(CONFIG_P1020UTM)
29 #define CONFIG_BOARDNAME "P1020UTM-PC"
31 #define __SW_BOOT_MASK 0x03
32 #define __SW_BOOT_NOR 0xe0
33 #define __SW_BOOT_SD 0x50
34 #define CONFIG_SYS_L2_SIZE (256 << 10)
37 #if defined(CONFIG_P1020RDB_PC)
38 #define CONFIG_BOARDNAME "P1020RDB-PC"
39 #define CONFIG_NAND_FSL_ELBC
41 #define CONFIG_SPI_FLASH
42 #define CONFIG_VSC7385_ENET
44 #define __SW_BOOT_MASK 0x03
45 #define __SW_BOOT_NOR 0x5c
46 #define __SW_BOOT_SPI 0x1c
47 #define __SW_BOOT_SD 0x9c
48 #define __SW_BOOT_NAND 0xec
49 #define __SW_BOOT_PCIE 0x6c
50 #define CONFIG_SYS_L2_SIZE (256 << 10)
54 * P1020RDB-PD board has user selectable switches for evaluating different
55 * frequency and boot options for the P1020 device. The table that
56 * follow describe the available options. The front six binary number was in
57 * accordance with SW3[1:6].
58 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
59 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
60 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
61 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
62 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
63 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
64 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
66 #if defined(CONFIG_P1020RDB_PD)
67 #define CONFIG_BOARDNAME "P1020RDB-PD"
68 #define CONFIG_NAND_FSL_ELBC
70 #define CONFIG_SPI_FLASH
71 #define CONFIG_VSC7385_ENET
73 #define __SW_BOOT_MASK 0x03
74 #define __SW_BOOT_NOR 0x64
75 #define __SW_BOOT_SPI 0x34
76 #define __SW_BOOT_SD 0x24
77 #define __SW_BOOT_NAND 0x44
78 #define __SW_BOOT_PCIE 0x74
79 #define CONFIG_SYS_L2_SIZE (256 << 10)
82 #if defined(CONFIG_P1021RDB)
83 #define CONFIG_BOARDNAME "P1021RDB-PC"
84 #define CONFIG_NAND_FSL_ELBC
87 #define CONFIG_SPI_FLASH
88 #define CONFIG_VSC7385_ENET
89 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
90 addresses in the LBC */
91 #define __SW_BOOT_MASK 0x03
92 #define __SW_BOOT_NOR 0x5c
93 #define __SW_BOOT_SPI 0x1c
94 #define __SW_BOOT_SD 0x9c
95 #define __SW_BOOT_NAND 0xec
96 #define __SW_BOOT_PCIE 0x6c
97 #define CONFIG_SYS_L2_SIZE (256 << 10)
100 #if defined(CONFIG_P1024RDB)
101 #define CONFIG_BOARDNAME "P1024RDB"
102 #define CONFIG_NAND_FSL_ELBC
105 #define CONFIG_SPI_FLASH
106 #define __SW_BOOT_MASK 0xf3
107 #define __SW_BOOT_NOR 0x00
108 #define __SW_BOOT_SPI 0x08
109 #define __SW_BOOT_SD 0x04
110 #define __SW_BOOT_NAND 0x0c
111 #define CONFIG_SYS_L2_SIZE (256 << 10)
114 #if defined(CONFIG_P1025RDB)
115 #define CONFIG_BOARDNAME "P1025RDB"
116 #define CONFIG_NAND_FSL_ELBC
120 #define CONFIG_SPI_FLASH
122 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
123 addresses in the LBC */
124 #define __SW_BOOT_MASK 0xf3
125 #define __SW_BOOT_NOR 0x00
126 #define __SW_BOOT_SPI 0x08
127 #define __SW_BOOT_SD 0x04
128 #define __SW_BOOT_NAND 0x0c
129 #define CONFIG_SYS_L2_SIZE (256 << 10)
132 #if defined(CONFIG_P2020RDB)
133 #define CONFIG_BOARDNAME "P2020RDB-PCA"
134 #define CONFIG_NAND_FSL_ELBC
136 #define CONFIG_SPI_FLASH
137 #define CONFIG_VSC7385_ENET
138 #define __SW_BOOT_MASK 0x03
139 #define __SW_BOOT_NOR 0xc8
140 #define __SW_BOOT_SPI 0x28
141 #define __SW_BOOT_SD 0x68 /* or 0x18 */
142 #define __SW_BOOT_NAND 0xe8
143 #define __SW_BOOT_PCIE 0xa8
144 #define CONFIG_SYS_L2_SIZE (512 << 10)
149 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
150 #define CONFIG_SPL_ENV_SUPPORT
151 #define CONFIG_SPL_SERIAL_SUPPORT
152 #define CONFIG_SPL_MMC_SUPPORT
153 #define CONFIG_SPL_MMC_MINIMAL
154 #define CONFIG_SPL_FLUSH_IMAGE
155 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
156 #define CONFIG_SPL_LIBGENERIC_SUPPORT
157 #define CONFIG_SPL_LIBCOMMON_SUPPORT
158 #define CONFIG_SPL_I2C_SUPPORT
159 #define CONFIG_FSL_LAW /* Use common FSL init code */
160 #define CONFIG_SYS_TEXT_BASE 0x11001000
161 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
162 #define CONFIG_SPL_PAD_TO 0x18000
163 #define CONFIG_SPL_MAX_SIZE (96 * 1024)
164 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
165 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
166 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
167 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
168 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
169 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
170 #define CONFIG_SPL_MMC_BOOT
171 #ifdef CONFIG_SPL_BUILD
172 #define CONFIG_SPL_COMMON_INIT_DDR
176 #ifdef CONFIG_SPIFLASH
178 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
179 #define CONFIG_SPL_ENV_SUPPORT
180 #define CONFIG_SPL_SERIAL_SUPPORT
181 #define CONFIG_SPL_SPI_SUPPORT
182 #define CONFIG_SPL_SPI_FLASH_SUPPORT
183 #define CONFIG_SPL_SPI_FLASH_MINIMAL
184 #define CONFIG_SPL_FLUSH_IMAGE
185 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
186 #define CONFIG_SPL_LIBGENERIC_SUPPORT
187 #define CONFIG_SPL_LIBCOMMON_SUPPORT
188 #define CONFIG_SPL_I2C_SUPPORT
189 #define CONFIG_FSL_LAW /* Use common FSL init code */
190 #define CONFIG_SYS_TEXT_BASE 0x11001000
191 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
192 #define CONFIG_SPL_PAD_TO 0x18000
193 #define CONFIG_SPL_MAX_SIZE (96 * 1024)
194 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
195 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
196 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
197 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
198 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
199 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
200 #define CONFIG_SPL_SPI_BOOT
201 #ifdef CONFIG_SPL_BUILD
202 #define CONFIG_SPL_COMMON_INIT_DDR
208 #define CONFIG_SPL_INIT_MINIMAL
209 #define CONFIG_SPL_SERIAL_SUPPORT
210 #define CONFIG_SPL_NAND_SUPPORT
211 #define CONFIG_SPL_FLUSH_IMAGE
212 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
214 #define CONFIG_SPL_TEXT_BASE 0xfffff000
215 #define CONFIG_SPL_MAX_SIZE 4096
217 #ifdef CONFIG_SYS_INIT_L2_ADDR
218 /* We multiply CONFIG_SPL_MAX_SIZE by two to leave some room for BSS. */
219 #define CONFIG_SYS_TEXT_BASE 0xf8f82000
220 #define CONFIG_SPL_RELOC_TEXT_BASE \
221 (CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2)
222 #define CONFIG_SPL_RELOC_STACK \
223 (CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2)
224 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
225 #define CONFIG_SYS_NAND_U_BOOT_START \
226 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SPL_MAX_SIZE)
228 #define CONFIG_SYS_TEXT_BASE 0x00201000
229 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
230 #define CONFIG_SPL_RELOC_STACK 0x00100000
231 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
232 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
235 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
236 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
237 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
240 #ifndef CONFIG_SYS_TEXT_BASE
241 #define CONFIG_SYS_TEXT_BASE 0xeff80000
244 #ifndef CONFIG_RESET_VECTOR_ADDRESS
245 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
248 #ifndef CONFIG_SYS_MONITOR_BASE
249 #ifdef CONFIG_SPL_BUILD
250 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
252 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
256 /* High Level Configuration Options */
259 #define CONFIG_MPC85xx
263 #define CONFIG_FSL_ELBC
265 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
266 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
267 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
268 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
269 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
270 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
272 #define CONFIG_FSL_LAW
273 #define CONFIG_TSEC_ENET /* tsec ethernet support */
274 #define CONFIG_ENV_OVERWRITE
276 #define CONFIG_CMD_SATA
277 #define CONFIG_SATA_SIL
278 #define CONFIG_SYS_SATA_MAX_DEVICE 2
279 #define CONFIG_LIBATA
282 #if defined(CONFIG_P2020RDB)
283 #define CONFIG_SYS_CLK_FREQ 100000000
285 #define CONFIG_SYS_CLK_FREQ 66666666
287 #define CONFIG_DDR_CLK_FREQ 66666666
289 #define CONFIG_HWCONFIG
291 * These can be toggled for performance analysis, otherwise use default.
293 #define CONFIG_L2_CACHE
296 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
298 #define CONFIG_ENABLE_36BIT_PHYS
300 #ifdef CONFIG_PHYS_64BIT
301 #define CONFIG_ADDR_MAP 1
302 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
305 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
306 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
307 #define CONFIG_PANIC_HANG /* do not reset board on panic */
309 #define CONFIG_SYS_CCSRBAR 0xffe00000
310 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
312 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
314 #ifdef CONFIG_SPL_BUILD
315 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
319 #define CONFIG_FSL_DDR3
320 #define CONFIG_SYS_DDR_RAW_TIMING
321 #define CONFIG_DDR_SPD
322 #define CONFIG_SYS_SPD_BUS_NUM 1
323 #define SPD_EEPROM_ADDRESS 0x52
324 #undef CONFIG_FSL_DDR_INTERACTIVE
326 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
327 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
328 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
330 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
331 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
333 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
334 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
335 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
337 #define CONFIG_NUM_DDR_CONTROLLERS 1
338 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
340 /* Default settings for DDR3 */
341 #ifndef CONFIG_P2020RDB
342 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
343 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
344 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
345 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
346 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
347 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
349 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
350 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
351 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
352 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
354 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
355 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
356 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
357 #define CONFIG_SYS_DDR_RCW_1 0x00000000
358 #define CONFIG_SYS_DDR_RCW_2 0x00000000
359 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
360 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
361 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
362 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
364 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
365 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
366 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
367 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
368 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
369 #define CONFIG_SYS_DDR_MODE_1 0x40461520
370 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
371 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
374 #undef CONFIG_CLOCKS_IN_MHZ
379 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
380 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
381 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
382 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
384 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
385 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
386 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
387 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
388 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
389 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
390 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
395 * Local Bus Definitions
397 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
398 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
399 #define CONFIG_SYS_FLASH_BASE 0xec000000
400 #elif defined(CONFIG_P1020UTM)
401 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
402 #define CONFIG_SYS_FLASH_BASE 0xee000000
404 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
405 #define CONFIG_SYS_FLASH_BASE 0xef000000
409 #ifdef CONFIG_PHYS_64BIT
410 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
412 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
415 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
418 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
420 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
421 #define CONFIG_SYS_FLASH_QUIET_TEST
422 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
424 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
426 #undef CONFIG_SYS_FLASH_CHECKSUM
427 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
428 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
430 #define CONFIG_FLASH_CFI_DRIVER
431 #define CONFIG_SYS_FLASH_CFI
432 #define CONFIG_SYS_FLASH_EMPTY_INFO
433 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
436 #ifdef CONFIG_NAND_FSL_ELBC
437 #define CONFIG_SYS_NAND_BASE 0xff800000
438 #ifdef CONFIG_PHYS_64BIT
439 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
441 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
444 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
445 #define CONFIG_SYS_MAX_NAND_DEVICE 1
446 #define CONFIG_MTD_NAND_VERIFY_WRITE
447 #define CONFIG_CMD_NAND
448 #if defined(CONFIG_P1020RDB_PD)
449 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
451 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
454 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
455 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
456 | BR_PS_8 /* Port Size = 8 bit */ \
457 | BR_MS_FCM /* MSEL = FCM */ \
459 #if defined(CONFIG_P1020RDB_PD)
460 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
461 | OR_FCM_PGS /* Large Page*/ \
469 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
477 #endif /* CONFIG_NAND_FSL_ELBC */
479 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
481 #define CONFIG_SYS_INIT_RAM_LOCK
482 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
483 #ifdef CONFIG_PHYS_64BIT
484 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
485 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
486 /* The assembler doesn't like typecast */
487 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
488 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
489 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
491 /* Initial L1 address */
492 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
493 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
494 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
496 /* Size of used area in RAM */
497 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
499 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
500 GENERATED_GBL_DATA_SIZE)
501 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
503 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
504 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
506 #define CONFIG_SYS_CPLD_BASE 0xffa00000
507 #ifdef CONFIG_PHYS_64BIT
508 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
510 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
512 /* CPLD config size: 1Mb */
513 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
515 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
517 #define CONFIG_SYS_PMC_BASE 0xff980000
518 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
519 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
521 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
522 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
526 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
527 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
528 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
529 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
531 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
532 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
533 #ifdef CONFIG_NAND_FSL_ELBC
534 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
535 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
538 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
539 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
543 #ifdef CONFIG_VSC7385_ENET
544 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
546 #ifdef CONFIG_PHYS_64BIT
547 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
549 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
552 #define CONFIG_SYS_VSC7385_BR_PRELIM \
553 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
554 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
555 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
556 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
558 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
559 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
561 /* The size of the VSC7385 firmware image */
562 #define CONFIG_VSC7385_IMAGE_SIZE 8192
566 * Config the L2 Cache as L2 SRAM
568 #if defined(CONFIG_SPL_BUILD)
569 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
570 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
571 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
572 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
573 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
574 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
575 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
576 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
577 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
578 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
582 /* Serial Port - controlled on board with jumper J8
586 #define CONFIG_CONS_INDEX 1
587 #undef CONFIG_SERIAL_SOFTWARE_FIFO
588 #define CONFIG_SYS_NS16550
589 #define CONFIG_SYS_NS16550_SERIAL
590 #define CONFIG_SYS_NS16550_REG_SIZE 1
591 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
592 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
593 #define CONFIG_NS16550_MIN_FUNCTIONS
596 #define CONFIG_SYS_BAUDRATE_TABLE \
597 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
599 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
600 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
602 /* Use the HUSH parser */
603 #define CONFIG_SYS_HUSH_PARSER
606 * Pass open firmware flat tree
608 #define CONFIG_OF_LIBFDT
609 #define CONFIG_OF_BOARD_SETUP
610 #define CONFIG_OF_STDOUT_VIA_ALIAS
612 /* new uImage format support */
614 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
617 #define CONFIG_SYS_I2C
618 #define CONFIG_SYS_I2C_FSL
619 #define CONFIG_SYS_FSL_I2C_SPEED 400000
620 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
621 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
622 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
623 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
624 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
625 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
626 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
627 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
632 #undef CONFIG_ID_EEPROM
634 #define CONFIG_RTC_PT7C4338
635 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
636 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
638 /* enable read and write access to EEPROM */
639 #define CONFIG_CMD_EEPROM
640 #define CONFIG_SYS_I2C_MULTI_EEPROMS
641 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
642 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
643 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
646 * eSPI - Enhanced SPI
648 #define CONFIG_HARD_SPI
649 #define CONFIG_FSL_ESPI
651 #if defined(CONFIG_SPI_FLASH)
652 #define CONFIG_SPI_FLASH_SPANSION
653 #define CONFIG_CMD_SF
654 #define CONFIG_SF_DEFAULT_SPEED 10000000
655 #define CONFIG_SF_DEFAULT_MODE 0
658 #if defined(CONFIG_PCI)
661 * Memory space is mapped 1-1, but I/O space must start from 0.
664 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
665 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
666 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
667 #ifdef CONFIG_PHYS_64BIT
668 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
669 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
671 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
672 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
674 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
675 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
676 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
677 #ifdef CONFIG_PHYS_64BIT
678 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
680 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
682 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
684 /* controller 1, Slot 2, tgtid 1, Base address a000 */
685 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
686 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
687 #ifdef CONFIG_PHYS_64BIT
688 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
689 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
691 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
692 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
694 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
695 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
696 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
697 #ifdef CONFIG_PHYS_64BIT
698 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
700 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
702 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
704 #define CONFIG_PCI_PNP /* do pci plug-and-play */
705 #define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/
706 #define CONFIG_CMD_PCI
707 #define CONFIG_CMD_NET
709 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
710 #define CONFIG_DOS_PARTITION
711 #endif /* CONFIG_PCI */
713 #if defined(CONFIG_TSEC_ENET)
714 #define CONFIG_MII /* MII PHY management */
716 #define CONFIG_TSEC1_NAME "eTSEC1"
718 #define CONFIG_TSEC2_NAME "eTSEC2"
720 #define CONFIG_TSEC3_NAME "eTSEC3"
722 #define TSEC1_PHY_ADDR 2
723 #define TSEC2_PHY_ADDR 0
724 #define TSEC3_PHY_ADDR 1
726 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
727 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
728 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
730 #define TSEC1_PHYIDX 0
731 #define TSEC2_PHYIDX 0
732 #define TSEC3_PHYIDX 0
734 #define CONFIG_ETHPRIME "eTSEC1"
736 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
738 #define CONFIG_HAS_ETH0
739 #define CONFIG_HAS_ETH1
740 #define CONFIG_HAS_ETH2
741 #endif /* CONFIG_TSEC_ENET */
744 /* QE microcode/firmware address */
745 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
746 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000
747 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
748 #endif /* CONFIG_QE */
750 #ifdef CONFIG_P1025RDB
752 * QE UEC ethernet configuration
754 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
756 #undef CONFIG_UEC_ETH
757 #define CONFIG_PHY_MODE_NEED_CHANGE
759 #define CONFIG_UEC_ETH1 /* ETH1 */
760 #define CONFIG_HAS_ETH0
762 #ifdef CONFIG_UEC_ETH1
763 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
764 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
765 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
766 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
767 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
768 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
769 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
770 #endif /* CONFIG_UEC_ETH1 */
772 #define CONFIG_UEC_ETH5 /* ETH5 */
773 #define CONFIG_HAS_ETH1
775 #ifdef CONFIG_UEC_ETH5
776 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
777 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
778 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
779 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
780 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
781 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
782 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
783 #endif /* CONFIG_UEC_ETH5 */
784 #endif /* CONFIG_P1025RDB */
789 #ifdef CONFIG_SPIFLASH
790 #define CONFIG_ENV_IS_IN_SPI_FLASH
791 #define CONFIG_ENV_SPI_BUS 0
792 #define CONFIG_ENV_SPI_CS 0
793 #define CONFIG_ENV_SPI_MAX_HZ 10000000
794 #define CONFIG_ENV_SPI_MODE 0
795 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
796 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
797 #define CONFIG_ENV_SECT_SIZE 0x10000
798 #elif defined(CONFIG_SDCARD)
799 #define CONFIG_ENV_IS_IN_MMC
800 #define CONFIG_FSL_FIXED_MMC_LOCATION
801 #define CONFIG_ENV_SIZE 0x2000
802 #define CONFIG_SYS_MMC_ENV_DEV 0
803 #elif defined(CONFIG_NAND)
804 #define CONFIG_ENV_IS_IN_NAND
805 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
806 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
807 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
808 #elif defined(CONFIG_SYS_RAMBOOT)
809 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
810 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
811 #define CONFIG_ENV_SIZE 0x2000
813 #define CONFIG_ENV_IS_IN_FLASH
814 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
815 #define CONFIG_ENV_ADDR 0xfff80000
817 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
819 #define CONFIG_ENV_SIZE 0x2000
820 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
823 #define CONFIG_LOADS_ECHO /* echo on for serial download */
824 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
827 * Command line configuration.
829 #include <config_cmd_default.h>
831 #define CONFIG_CMD_IRQ
832 #define CONFIG_CMD_PING
833 #define CONFIG_CMD_I2C
834 #define CONFIG_CMD_MII
835 #define CONFIG_CMD_DATE
836 #define CONFIG_CMD_ELF
837 #define CONFIG_CMD_SETEXPR
838 #define CONFIG_CMD_REGINFO
843 #define CONFIG_HAS_FSL_DR_USB
845 #if defined(CONFIG_HAS_FSL_DR_USB)
846 #define CONFIG_USB_EHCI
848 #ifdef CONFIG_USB_EHCI
849 #define CONFIG_CMD_USB
850 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
851 #define CONFIG_USB_EHCI_FSL
852 #define CONFIG_USB_STORAGE
859 #define CONFIG_FSL_ESDHC
860 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
861 #define CONFIG_CMD_MMC
862 #define CONFIG_GENERIC_MMC
865 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
866 || defined(CONFIG_FSL_SATA)
867 #define CONFIG_CMD_EXT2
868 #define CONFIG_CMD_FAT
869 #define CONFIG_DOS_PARTITION
872 #undef CONFIG_WATCHDOG /* watchdog disabled */
875 * Miscellaneous configurable options
877 #define CONFIG_SYS_LONGHELP /* undef to save memory */
878 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
879 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
880 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
881 #if defined(CONFIG_CMD_KGDB)
882 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
884 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
886 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
887 /* Print Buffer Size */
888 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
889 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
890 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
893 * For booting Linux, the board info and command line data
894 * have to be in the first 64 MB of memory, since this is
895 * the maximum mapped by the Linux kernel during initialization.
897 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
898 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
900 #if defined(CONFIG_CMD_KGDB)
901 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
902 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
906 * Environment Configuration
908 #define CONFIG_HOSTNAME unknown
909 #define CONFIG_ROOTPATH "/opt/nfsroot"
910 #define CONFIG_BOOTFILE "uImage"
911 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
913 /* default location for tftp and bootm */
914 #define CONFIG_LOADADDR 1000000
916 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
917 #define CONFIG_BOOTARGS /* the boot command will set bootargs */
919 #define CONFIG_BAUDRATE 115200
922 #define __NOR_RST_CMD \
923 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
924 i2c mw 18 3 __SW_BOOT_MASK 1; reset
927 #define __SPI_RST_CMD \
928 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
929 i2c mw 18 3 __SW_BOOT_MASK 1; reset
932 #define __SD_RST_CMD \
933 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
934 i2c mw 18 3 __SW_BOOT_MASK 1; reset
936 #ifdef __SW_BOOT_NAND
937 #define __NAND_RST_CMD \
938 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
939 i2c mw 18 3 __SW_BOOT_MASK 1; reset
941 #ifdef __SW_BOOT_PCIE
942 #define __PCIE_RST_CMD \
943 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
944 i2c mw 18 3 __SW_BOOT_MASK 1; reset
947 #define CONFIG_EXTRA_ENV_SETTINGS \
949 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
950 "loadaddr=1000000\0" \
951 "bootfile=uImage\0" \
952 "tftpflash=tftpboot $loadaddr $uboot; " \
953 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
954 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
955 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
956 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
957 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
958 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
959 "consoledev=ttyS0\0" \
960 "ramdiskaddr=2000000\0" \
961 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
964 "jffs2nor=mtdblock3\0" \
965 "norbootaddr=ef080000\0" \
966 "norfdtaddr=ef040000\0" \
967 "jffs2nand=mtdblock9\0" \
968 "nandbootaddr=100000\0" \
969 "nandfdtaddr=80000\0" \
970 "ramdisk_size=120000\0" \
971 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
972 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
973 __stringify(__NOR_RST_CMD)"\0" \
974 __stringify(__SPI_RST_CMD)"\0" \
975 __stringify(__SD_RST_CMD)"\0" \
976 __stringify(__NAND_RST_CMD)"\0" \
977 __stringify(__PCIE_RST_CMD)"\0"
979 #define CONFIG_NFSBOOTCOMMAND \
980 "setenv bootargs root=/dev/nfs rw " \
981 "nfsroot=$serverip:$rootpath " \
982 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
983 "console=$consoledev,$baudrate $othbootargs;" \
984 "tftp $loadaddr $bootfile;" \
985 "tftp $fdtaddr $fdtfile;" \
986 "bootm $loadaddr - $fdtaddr"
988 #define CONFIG_HDBOOT \
989 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
990 "console=$consoledev,$baudrate $othbootargs;" \
992 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
993 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
994 "bootm $loadaddr - $fdtaddr"
996 #define CONFIG_USB_FAT_BOOT \
997 "setenv bootargs root=/dev/ram rw " \
998 "console=$consoledev,$baudrate $othbootargs " \
999 "ramdisk_size=$ramdisk_size;" \
1001 "fatload usb 0:2 $loadaddr $bootfile;" \
1002 "fatload usb 0:2 $fdtaddr $fdtfile;" \
1003 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
1004 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1006 #define CONFIG_USB_EXT2_BOOT \
1007 "setenv bootargs root=/dev/ram rw " \
1008 "console=$consoledev,$baudrate $othbootargs " \
1009 "ramdisk_size=$ramdisk_size;" \
1011 "ext2load usb 0:4 $loadaddr $bootfile;" \
1012 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
1013 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
1014 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1016 #define CONFIG_NORBOOT \
1017 "setenv bootargs root=/dev/$jffs2nor rw " \
1018 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
1019 "bootm $norbootaddr - $norfdtaddr"
1021 #define CONFIG_RAMBOOTCOMMAND \
1022 "setenv bootargs root=/dev/ram rw " \
1023 "console=$consoledev,$baudrate $othbootargs " \
1024 "ramdisk_size=$ramdisk_size;" \
1025 "tftp $ramdiskaddr $ramdiskfile;" \
1026 "tftp $loadaddr $bootfile;" \
1027 "tftp $fdtaddr $fdtfile;" \
1028 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1030 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
1032 #endif /* __CONFIG_H */