2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * QorIQ RDB boards configuration file
13 #if defined(CONFIG_TARGET_P1020MBG)
14 #define CONFIG_BOARDNAME "P1020MBG-PC"
15 #define CONFIG_VSC7385_ENET
17 #define __SW_BOOT_MASK 0x03
18 #define __SW_BOOT_NOR 0xe4
19 #define __SW_BOOT_SD 0x54
20 #define CONFIG_SYS_L2_SIZE (256 << 10)
23 #if defined(CONFIG_TARGET_P1020UTM)
24 #define CONFIG_BOARDNAME "P1020UTM-PC"
25 #define __SW_BOOT_MASK 0x03
26 #define __SW_BOOT_NOR 0xe0
27 #define __SW_BOOT_SD 0x50
28 #define CONFIG_SYS_L2_SIZE (256 << 10)
31 #if defined(CONFIG_TARGET_P1020RDB_PC)
32 #define CONFIG_BOARDNAME "P1020RDB-PC"
33 #define CONFIG_NAND_FSL_ELBC
34 #define CONFIG_VSC7385_ENET
36 #define __SW_BOOT_MASK 0x03
37 #define __SW_BOOT_NOR 0x5c
38 #define __SW_BOOT_SPI 0x1c
39 #define __SW_BOOT_SD 0x9c
40 #define __SW_BOOT_NAND 0xec
41 #define __SW_BOOT_PCIE 0x6c
42 #define CONFIG_SYS_L2_SIZE (256 << 10)
46 * P1020RDB-PD board has user selectable switches for evaluating different
47 * frequency and boot options for the P1020 device. The table that
48 * follow describe the available options. The front six binary number was in
49 * accordance with SW3[1:6].
50 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
51 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
52 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
53 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
54 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
55 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
56 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
58 #if defined(CONFIG_TARGET_P1020RDB_PD)
59 #define CONFIG_BOARDNAME "P1020RDB-PD"
60 #define CONFIG_NAND_FSL_ELBC
61 #define CONFIG_VSC7385_ENET
63 #define __SW_BOOT_MASK 0x03
64 #define __SW_BOOT_NOR 0x64
65 #define __SW_BOOT_SPI 0x34
66 #define __SW_BOOT_SD 0x24
67 #define __SW_BOOT_NAND 0x44
68 #define __SW_BOOT_PCIE 0x74
69 #define CONFIG_SYS_L2_SIZE (256 << 10)
71 * Dynamic MTD Partition support with mtdparts
73 #define CONFIG_MTD_DEVICE
74 #define CONFIG_MTD_PARTITIONS
75 #define CONFIG_FLASH_CFI_MTD
78 #if defined(CONFIG_TARGET_P1021RDB)
79 #define CONFIG_BOARDNAME "P1021RDB-PC"
80 #define CONFIG_NAND_FSL_ELBC
82 #define CONFIG_VSC7385_ENET
83 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
84 addresses in the LBC */
85 #define __SW_BOOT_MASK 0x03
86 #define __SW_BOOT_NOR 0x5c
87 #define __SW_BOOT_SPI 0x1c
88 #define __SW_BOOT_SD 0x9c
89 #define __SW_BOOT_NAND 0xec
90 #define __SW_BOOT_PCIE 0x6c
91 #define CONFIG_SYS_L2_SIZE (256 << 10)
93 * Dynamic MTD Partition support with mtdparts
95 #define CONFIG_MTD_DEVICE
96 #define CONFIG_MTD_PARTITIONS
97 #define CONFIG_FLASH_CFI_MTD
100 #if defined(CONFIG_TARGET_P1024RDB)
101 #define CONFIG_BOARDNAME "P1024RDB"
102 #define CONFIG_NAND_FSL_ELBC
104 #define __SW_BOOT_MASK 0xf3
105 #define __SW_BOOT_NOR 0x00
106 #define __SW_BOOT_SPI 0x08
107 #define __SW_BOOT_SD 0x04
108 #define __SW_BOOT_NAND 0x0c
109 #define CONFIG_SYS_L2_SIZE (256 << 10)
112 #if defined(CONFIG_TARGET_P1025RDB)
113 #define CONFIG_BOARDNAME "P1025RDB"
114 #define CONFIG_NAND_FSL_ELBC
118 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
119 addresses in the LBC */
120 #define __SW_BOOT_MASK 0xf3
121 #define __SW_BOOT_NOR 0x00
122 #define __SW_BOOT_SPI 0x08
123 #define __SW_BOOT_SD 0x04
124 #define __SW_BOOT_NAND 0x0c
125 #define CONFIG_SYS_L2_SIZE (256 << 10)
128 #if defined(CONFIG_TARGET_P2020RDB)
129 #define CONFIG_BOARDNAME "P2020RDB-PC"
130 #define CONFIG_NAND_FSL_ELBC
131 #define CONFIG_VSC7385_ENET
132 #define __SW_BOOT_MASK 0x03
133 #define __SW_BOOT_NOR 0xc8
134 #define __SW_BOOT_SPI 0x28
135 #define __SW_BOOT_SD 0x68 /* or 0x18 */
136 #define __SW_BOOT_NAND 0xe8
137 #define __SW_BOOT_PCIE 0xa8
138 #define CONFIG_SYS_L2_SIZE (512 << 10)
140 * Dynamic MTD Partition support with mtdparts
142 #define CONFIG_MTD_DEVICE
143 #define CONFIG_MTD_PARTITIONS
144 #define CONFIG_FLASH_CFI_MTD
148 #define CONFIG_SPL_MMC_MINIMAL
149 #define CONFIG_SPL_FLUSH_IMAGE
150 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
151 #define CONFIG_SYS_TEXT_BASE 0x11001000
152 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
153 #define CONFIG_SPL_PAD_TO 0x20000
154 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
155 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
156 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
157 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
158 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
159 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
160 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
161 #define CONFIG_SPL_MMC_BOOT
162 #ifdef CONFIG_SPL_BUILD
163 #define CONFIG_SPL_COMMON_INIT_DDR
167 #ifdef CONFIG_SPIFLASH
168 #define CONFIG_SPL_SPI_FLASH_MINIMAL
169 #define CONFIG_SPL_FLUSH_IMAGE
170 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
171 #define CONFIG_SYS_TEXT_BASE 0x11001000
172 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
173 #define CONFIG_SPL_PAD_TO 0x20000
174 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
175 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
176 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
177 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
178 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
179 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
180 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
181 #define CONFIG_SPL_SPI_BOOT
182 #ifdef CONFIG_SPL_BUILD
183 #define CONFIG_SPL_COMMON_INIT_DDR
188 #ifdef CONFIG_TPL_BUILD
189 #define CONFIG_SPL_NAND_BOOT
190 #define CONFIG_SPL_FLUSH_IMAGE
191 #define CONFIG_SPL_NAND_INIT
192 #define CONFIG_SPL_COMMON_INIT_DDR
193 #define CONFIG_SPL_MAX_SIZE (128 << 10)
194 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
195 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
196 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
197 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
198 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
199 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
200 #elif defined(CONFIG_SPL_BUILD)
201 #define CONFIG_SPL_INIT_MINIMAL
202 #define CONFIG_SPL_FLUSH_IMAGE
203 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
204 #define CONFIG_SPL_TEXT_BASE 0xff800000
205 #define CONFIG_SPL_MAX_SIZE 4096
206 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
207 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
208 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
209 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
210 #endif /* not CONFIG_TPL_BUILD */
212 #define CONFIG_SPL_PAD_TO 0x20000
213 #define CONFIG_TPL_PAD_TO 0x20000
214 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
215 #define CONFIG_SYS_TEXT_BASE 0x11001000
216 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
219 #ifndef CONFIG_SYS_TEXT_BASE
220 #define CONFIG_SYS_TEXT_BASE 0xeff40000
223 #ifndef CONFIG_RESET_VECTOR_ADDRESS
224 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
227 #ifndef CONFIG_SYS_MONITOR_BASE
228 #ifdef CONFIG_SPL_BUILD
229 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
231 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
237 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
238 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
239 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
240 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
241 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
242 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
244 #define CONFIG_TSEC_ENET /* tsec ethernet support */
245 #define CONFIG_ENV_OVERWRITE
247 #define CONFIG_SYS_SATA_MAX_DEVICE 2
248 #define CONFIG_LIBATA
251 #if defined(CONFIG_TARGET_P2020RDB)
252 #define CONFIG_SYS_CLK_FREQ 100000000
254 #define CONFIG_SYS_CLK_FREQ 66666666
256 #define CONFIG_DDR_CLK_FREQ 66666666
258 #define CONFIG_HWCONFIG
260 * These can be toggled for performance analysis, otherwise use default.
262 #define CONFIG_L2_CACHE
265 #define CONFIG_ENABLE_36BIT_PHYS
267 #ifdef CONFIG_PHYS_64BIT
268 #define CONFIG_ADDR_MAP 1
269 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
272 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
273 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
274 #define CONFIG_PANIC_HANG /* do not reset board on panic */
276 #define CONFIG_SYS_CCSRBAR 0xffe00000
277 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
279 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
281 #ifdef CONFIG_SPL_BUILD
282 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
286 #define CONFIG_SYS_DDR_RAW_TIMING
287 #define CONFIG_DDR_SPD
288 #define CONFIG_SYS_SPD_BUS_NUM 1
289 #define SPD_EEPROM_ADDRESS 0x52
290 #undef CONFIG_FSL_DDR_INTERACTIVE
292 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
293 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
294 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
296 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
297 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
299 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
300 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
301 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
303 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
305 /* Default settings for DDR3 */
306 #ifndef CONFIG_TARGET_P2020RDB
307 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
308 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
309 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
310 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
311 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
312 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
314 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
315 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
316 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
317 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
319 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
320 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
321 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
322 #define CONFIG_SYS_DDR_RCW_1 0x00000000
323 #define CONFIG_SYS_DDR_RCW_2 0x00000000
324 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
325 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
326 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
327 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
329 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
330 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
331 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
332 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
333 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
334 #define CONFIG_SYS_DDR_MODE_1 0x40461520
335 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
336 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
339 #undef CONFIG_CLOCKS_IN_MHZ
344 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
345 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
346 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
347 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
349 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
350 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
351 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
352 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
353 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
354 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
355 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
359 * Local Bus Definitions
361 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
362 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
363 #define CONFIG_SYS_FLASH_BASE 0xec000000
364 #elif defined(CONFIG_TARGET_P1020UTM)
365 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
366 #define CONFIG_SYS_FLASH_BASE 0xee000000
368 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
369 #define CONFIG_SYS_FLASH_BASE 0xef000000
372 #ifdef CONFIG_PHYS_64BIT
373 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
375 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
378 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
381 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
383 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
384 #define CONFIG_SYS_FLASH_QUIET_TEST
385 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
387 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
389 #undef CONFIG_SYS_FLASH_CHECKSUM
390 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
391 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
393 #define CONFIG_FLASH_CFI_DRIVER
394 #define CONFIG_SYS_FLASH_CFI
395 #define CONFIG_SYS_FLASH_EMPTY_INFO
396 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
399 #ifdef CONFIG_NAND_FSL_ELBC
400 #define CONFIG_SYS_NAND_BASE 0xff800000
401 #ifdef CONFIG_PHYS_64BIT
402 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
404 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
407 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
408 #define CONFIG_SYS_MAX_NAND_DEVICE 1
409 #if defined(CONFIG_TARGET_P1020RDB_PD)
410 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
412 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
415 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
416 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
417 | BR_PS_8 /* Port Size = 8 bit */ \
418 | BR_MS_FCM /* MSEL = FCM */ \
420 #if defined(CONFIG_TARGET_P1020RDB_PD)
421 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
422 | OR_FCM_PGS /* Large Page*/ \
430 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
438 #endif /* CONFIG_NAND_FSL_ELBC */
440 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
442 #define CONFIG_SYS_INIT_RAM_LOCK
443 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
444 #ifdef CONFIG_PHYS_64BIT
445 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
446 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
447 /* The assembler doesn't like typecast */
448 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
449 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
450 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
452 /* Initial L1 address */
453 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
454 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
455 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
457 /* Size of used area in RAM */
458 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
460 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
461 GENERATED_GBL_DATA_SIZE)
462 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
464 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
465 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
467 #define CONFIG_SYS_CPLD_BASE 0xffa00000
468 #ifdef CONFIG_PHYS_64BIT
469 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
471 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
473 /* CPLD config size: 1Mb */
474 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
476 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
478 #define CONFIG_SYS_PMC_BASE 0xff980000
479 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
480 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
482 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
483 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
487 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
488 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
489 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
490 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
492 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
493 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
494 #ifdef CONFIG_NAND_FSL_ELBC
495 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
496 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
499 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
500 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
503 #ifdef CONFIG_VSC7385_ENET
504 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
506 #ifdef CONFIG_PHYS_64BIT
507 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
509 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
512 #define CONFIG_SYS_VSC7385_BR_PRELIM \
513 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
514 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
515 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
516 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
518 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
519 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
521 /* The size of the VSC7385 firmware image */
522 #define CONFIG_VSC7385_IMAGE_SIZE 8192
526 * Config the L2 Cache as L2 SRAM
528 #if defined(CONFIG_SPL_BUILD)
529 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
530 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
531 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
532 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
533 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
534 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
535 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
536 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
537 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
538 #if defined(CONFIG_TARGET_P2020RDB)
539 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
541 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
543 #elif defined(CONFIG_NAND)
544 #ifdef CONFIG_TPL_BUILD
545 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
546 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
547 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
548 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
549 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
550 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
551 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
552 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
554 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
555 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
556 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
557 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
558 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
559 #endif /* CONFIG_TPL_BUILD */
563 /* Serial Port - controlled on board with jumper J8
567 #define CONFIG_CONS_INDEX 1
568 #undef CONFIG_SERIAL_SOFTWARE_FIFO
569 #define CONFIG_SYS_NS16550_SERIAL
570 #define CONFIG_SYS_NS16550_REG_SIZE 1
571 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
572 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
573 #define CONFIG_NS16550_MIN_FUNCTIONS
576 #define CONFIG_SYS_BAUDRATE_TABLE \
577 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
579 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
580 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
583 #define CONFIG_SYS_I2C
584 #define CONFIG_SYS_I2C_FSL
585 #define CONFIG_SYS_FSL_I2C_SPEED 400000
586 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
587 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
588 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
589 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
590 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
591 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
592 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
593 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
598 #undef CONFIG_ID_EEPROM
600 #define CONFIG_RTC_PT7C4338
601 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
602 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
604 /* enable read and write access to EEPROM */
605 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
606 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
607 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
610 * eSPI - Enhanced SPI
612 #define CONFIG_HARD_SPI
614 #if defined(CONFIG_SPI_FLASH)
615 #define CONFIG_SF_DEFAULT_SPEED 10000000
616 #define CONFIG_SF_DEFAULT_MODE 0
619 #if defined(CONFIG_PCI)
622 * Memory space is mapped 1-1, but I/O space must start from 0.
625 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
626 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
627 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
628 #ifdef CONFIG_PHYS_64BIT
629 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
630 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
632 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
633 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
635 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
636 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
637 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
638 #ifdef CONFIG_PHYS_64BIT
639 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
641 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
643 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
645 /* controller 1, Slot 2, tgtid 1, Base address a000 */
646 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
647 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
648 #ifdef CONFIG_PHYS_64BIT
649 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
650 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
652 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
653 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
655 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
656 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
657 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
658 #ifdef CONFIG_PHYS_64BIT
659 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
661 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
663 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
665 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
666 #endif /* CONFIG_PCI */
668 #if defined(CONFIG_TSEC_ENET)
669 #define CONFIG_MII /* MII PHY management */
671 #define CONFIG_TSEC1_NAME "eTSEC1"
673 #define CONFIG_TSEC2_NAME "eTSEC2"
675 #define CONFIG_TSEC3_NAME "eTSEC3"
677 #define TSEC1_PHY_ADDR 2
678 #define TSEC2_PHY_ADDR 0
679 #define TSEC3_PHY_ADDR 1
681 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
682 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
683 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
685 #define TSEC1_PHYIDX 0
686 #define TSEC2_PHYIDX 0
687 #define TSEC3_PHYIDX 0
689 #define CONFIG_ETHPRIME "eTSEC1"
691 #define CONFIG_HAS_ETH0
692 #define CONFIG_HAS_ETH1
693 #define CONFIG_HAS_ETH2
694 #endif /* CONFIG_TSEC_ENET */
697 /* QE microcode/firmware address */
698 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
699 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
700 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
701 #endif /* CONFIG_QE */
703 #ifdef CONFIG_TARGET_P1025RDB
705 * QE UEC ethernet configuration
707 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
709 #undef CONFIG_UEC_ETH
710 #define CONFIG_PHY_MODE_NEED_CHANGE
712 #define CONFIG_UEC_ETH1 /* ETH1 */
713 #define CONFIG_HAS_ETH0
715 #ifdef CONFIG_UEC_ETH1
716 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
717 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
718 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
719 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
720 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
721 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
722 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
723 #endif /* CONFIG_UEC_ETH1 */
725 #define CONFIG_UEC_ETH5 /* ETH5 */
726 #define CONFIG_HAS_ETH1
728 #ifdef CONFIG_UEC_ETH5
729 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
730 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
731 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
732 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
733 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
734 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
735 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
736 #endif /* CONFIG_UEC_ETH5 */
737 #endif /* CONFIG_TARGET_P1025RDB */
742 #ifdef CONFIG_SPIFLASH
743 #define CONFIG_ENV_SPI_BUS 0
744 #define CONFIG_ENV_SPI_CS 0
745 #define CONFIG_ENV_SPI_MAX_HZ 10000000
746 #define CONFIG_ENV_SPI_MODE 0
747 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
748 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
749 #define CONFIG_ENV_SECT_SIZE 0x10000
750 #elif defined(CONFIG_SDCARD)
751 #define CONFIG_FSL_FIXED_MMC_LOCATION
752 #define CONFIG_ENV_SIZE 0x2000
753 #define CONFIG_SYS_MMC_ENV_DEV 0
754 #elif defined(CONFIG_NAND)
755 #ifdef CONFIG_TPL_BUILD
756 #define CONFIG_ENV_SIZE 0x2000
757 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
759 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
761 #define CONFIG_ENV_OFFSET (1024 * 1024)
762 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
763 #elif defined(CONFIG_SYS_RAMBOOT)
764 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
765 #define CONFIG_ENV_SIZE 0x2000
767 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
768 #define CONFIG_ENV_SIZE 0x2000
769 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
772 #define CONFIG_LOADS_ECHO /* echo on for serial download */
773 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
778 #define CONFIG_HAS_FSL_DR_USB
780 #if defined(CONFIG_HAS_FSL_DR_USB)
781 #ifdef CONFIG_USB_EHCI_HCD
782 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
783 #define CONFIG_USB_EHCI_FSL
784 #define CONFIG_EHCI_DESC_BIG_ENDIAN
788 #if defined(CONFIG_TARGET_P1020RDB_PD)
789 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
793 #define CONFIG_FSL_ESDHC
794 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
797 #undef CONFIG_WATCHDOG /* watchdog disabled */
800 * Miscellaneous configurable options
802 #define CONFIG_SYS_LONGHELP /* undef to save memory */
803 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
804 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
807 * For booting Linux, the board info and command line data
808 * have to be in the first 64 MB of memory, since this is
809 * the maximum mapped by the Linux kernel during initialization.
811 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
812 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
814 #if defined(CONFIG_CMD_KGDB)
815 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
819 * Environment Configuration
821 #define CONFIG_HOSTNAME unknown
822 #define CONFIG_ROOTPATH "/opt/nfsroot"
823 #define CONFIG_BOOTFILE "uImage"
824 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
826 /* default location for tftp and bootm */
827 #define CONFIG_LOADADDR 1000000
830 #define __NOR_RST_CMD \
831 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
832 i2c mw 18 3 __SW_BOOT_MASK 1; reset
835 #define __SPI_RST_CMD \
836 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
837 i2c mw 18 3 __SW_BOOT_MASK 1; reset
840 #define __SD_RST_CMD \
841 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
842 i2c mw 18 3 __SW_BOOT_MASK 1; reset
844 #ifdef __SW_BOOT_NAND
845 #define __NAND_RST_CMD \
846 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
847 i2c mw 18 3 __SW_BOOT_MASK 1; reset
849 #ifdef __SW_BOOT_PCIE
850 #define __PCIE_RST_CMD \
851 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
852 i2c mw 18 3 __SW_BOOT_MASK 1; reset
855 #define CONFIG_EXTRA_ENV_SETTINGS \
857 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
858 "loadaddr=1000000\0" \
859 "bootfile=uImage\0" \
860 "tftpflash=tftpboot $loadaddr $uboot; " \
861 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
862 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
863 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
864 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
865 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
866 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
867 "consoledev=ttyS0\0" \
868 "ramdiskaddr=2000000\0" \
869 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
870 "fdtaddr=1e00000\0" \
872 "jffs2nor=mtdblock3\0" \
873 "norbootaddr=ef080000\0" \
874 "norfdtaddr=ef040000\0" \
875 "jffs2nand=mtdblock9\0" \
876 "nandbootaddr=100000\0" \
877 "nandfdtaddr=80000\0" \
878 "ramdisk_size=120000\0" \
879 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
880 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
881 __stringify(__NOR_RST_CMD)"\0" \
882 __stringify(__SPI_RST_CMD)"\0" \
883 __stringify(__SD_RST_CMD)"\0" \
884 __stringify(__NAND_RST_CMD)"\0" \
885 __stringify(__PCIE_RST_CMD)"\0"
887 #define CONFIG_NFSBOOTCOMMAND \
888 "setenv bootargs root=/dev/nfs rw " \
889 "nfsroot=$serverip:$rootpath " \
890 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
891 "console=$consoledev,$baudrate $othbootargs;" \
892 "tftp $loadaddr $bootfile;" \
893 "tftp $fdtaddr $fdtfile;" \
894 "bootm $loadaddr - $fdtaddr"
896 #define CONFIG_HDBOOT \
897 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
898 "console=$consoledev,$baudrate $othbootargs;" \
900 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
901 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
902 "bootm $loadaddr - $fdtaddr"
904 #define CONFIG_USB_FAT_BOOT \
905 "setenv bootargs root=/dev/ram rw " \
906 "console=$consoledev,$baudrate $othbootargs " \
907 "ramdisk_size=$ramdisk_size;" \
909 "fatload usb 0:2 $loadaddr $bootfile;" \
910 "fatload usb 0:2 $fdtaddr $fdtfile;" \
911 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
912 "bootm $loadaddr $ramdiskaddr $fdtaddr"
914 #define CONFIG_USB_EXT2_BOOT \
915 "setenv bootargs root=/dev/ram rw " \
916 "console=$consoledev,$baudrate $othbootargs " \
917 "ramdisk_size=$ramdisk_size;" \
919 "ext2load usb 0:4 $loadaddr $bootfile;" \
920 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
921 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
922 "bootm $loadaddr $ramdiskaddr $fdtaddr"
924 #define CONFIG_NORBOOT \
925 "setenv bootargs root=/dev/$jffs2nor rw " \
926 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
927 "bootm $norbootaddr - $norfdtaddr"
929 #define CONFIG_RAMBOOTCOMMAND \
930 "setenv bootargs root=/dev/ram rw " \
931 "console=$consoledev,$baudrate $othbootargs " \
932 "ramdisk_size=$ramdisk_size;" \
933 "tftp $ramdiskaddr $ramdiskfile;" \
934 "tftp $loadaddr $bootfile;" \
935 "tftp $fdtaddr $fdtfile;" \
936 "bootm $loadaddr $ramdiskaddr $fdtaddr"
938 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
940 #endif /* __CONFIG_H */