2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * QorIQ RDB boards configuration file
13 #if defined(CONFIG_TARGET_P1020MBG)
14 #define CONFIG_BOARDNAME "P1020MBG-PC"
15 #define CONFIG_VSC7385_ENET
17 #define __SW_BOOT_MASK 0x03
18 #define __SW_BOOT_NOR 0xe4
19 #define __SW_BOOT_SD 0x54
20 #define CONFIG_SYS_L2_SIZE (256 << 10)
23 #if defined(CONFIG_TARGET_P1020UTM)
24 #define CONFIG_BOARDNAME "P1020UTM-PC"
25 #define __SW_BOOT_MASK 0x03
26 #define __SW_BOOT_NOR 0xe0
27 #define __SW_BOOT_SD 0x50
28 #define CONFIG_SYS_L2_SIZE (256 << 10)
31 #if defined(CONFIG_TARGET_P1020RDB_PC)
32 #define CONFIG_BOARDNAME "P1020RDB-PC"
33 #define CONFIG_NAND_FSL_ELBC
34 #define CONFIG_VSC7385_ENET
36 #define __SW_BOOT_MASK 0x03
37 #define __SW_BOOT_NOR 0x5c
38 #define __SW_BOOT_SPI 0x1c
39 #define __SW_BOOT_SD 0x9c
40 #define __SW_BOOT_NAND 0xec
41 #define __SW_BOOT_PCIE 0x6c
42 #define CONFIG_SYS_L2_SIZE (256 << 10)
46 * P1020RDB-PD board has user selectable switches for evaluating different
47 * frequency and boot options for the P1020 device. The table that
48 * follow describe the available options. The front six binary number was in
49 * accordance with SW3[1:6].
50 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
51 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
52 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
53 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
54 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
55 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
56 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
58 #if defined(CONFIG_TARGET_P1020RDB_PD)
59 #define CONFIG_BOARDNAME "P1020RDB-PD"
60 #define CONFIG_NAND_FSL_ELBC
61 #define CONFIG_VSC7385_ENET
63 #define __SW_BOOT_MASK 0x03
64 #define __SW_BOOT_NOR 0x64
65 #define __SW_BOOT_SPI 0x34
66 #define __SW_BOOT_SD 0x24
67 #define __SW_BOOT_NAND 0x44
68 #define __SW_BOOT_PCIE 0x74
69 #define CONFIG_SYS_L2_SIZE (256 << 10)
71 * Dynamic MTD Partition support with mtdparts
73 #define CONFIG_MTD_DEVICE
74 #define CONFIG_MTD_PARTITIONS
75 #define CONFIG_CMD_MTDPARTS
76 #define CONFIG_FLASH_CFI_MTD
77 #define MTDIDS_DEFAULT "nor0=ec000000.nor"
78 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \
79 "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
82 #if defined(CONFIG_TARGET_P1021RDB)
83 #define CONFIG_BOARDNAME "P1021RDB-PC"
84 #define CONFIG_NAND_FSL_ELBC
86 #define CONFIG_VSC7385_ENET
87 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
88 addresses in the LBC */
89 #define __SW_BOOT_MASK 0x03
90 #define __SW_BOOT_NOR 0x5c
91 #define __SW_BOOT_SPI 0x1c
92 #define __SW_BOOT_SD 0x9c
93 #define __SW_BOOT_NAND 0xec
94 #define __SW_BOOT_PCIE 0x6c
95 #define CONFIG_SYS_L2_SIZE (256 << 10)
97 * Dynamic MTD Partition support with mtdparts
99 #define CONFIG_MTD_DEVICE
100 #define CONFIG_MTD_PARTITIONS
101 #define CONFIG_CMD_MTDPARTS
102 #define CONFIG_FLASH_CFI_MTD
103 #ifdef CONFIG_PHYS_64BIT
104 #define MTDIDS_DEFAULT "nor0=fef000000.nor"
105 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
106 "256k(dtb),4608k(kernel),9728k(fs)," \
107 "256k(qe-ucode-firmware),1280k(u-boot)"
109 #define MTDIDS_DEFAULT "nor0=ef000000.nor"
110 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
111 "256k(dtb),4608k(kernel),9728k(fs)," \
112 "256k(qe-ucode-firmware),1280k(u-boot)"
116 #if defined(CONFIG_TARGET_P1024RDB)
117 #define CONFIG_BOARDNAME "P1024RDB"
118 #define CONFIG_NAND_FSL_ELBC
120 #define __SW_BOOT_MASK 0xf3
121 #define __SW_BOOT_NOR 0x00
122 #define __SW_BOOT_SPI 0x08
123 #define __SW_BOOT_SD 0x04
124 #define __SW_BOOT_NAND 0x0c
125 #define CONFIG_SYS_L2_SIZE (256 << 10)
128 #if defined(CONFIG_TARGET_P1025RDB)
129 #define CONFIG_BOARDNAME "P1025RDB"
130 #define CONFIG_NAND_FSL_ELBC
134 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
135 addresses in the LBC */
136 #define __SW_BOOT_MASK 0xf3
137 #define __SW_BOOT_NOR 0x00
138 #define __SW_BOOT_SPI 0x08
139 #define __SW_BOOT_SD 0x04
140 #define __SW_BOOT_NAND 0x0c
141 #define CONFIG_SYS_L2_SIZE (256 << 10)
144 #if defined(CONFIG_TARGET_P2020RDB)
145 #define CONFIG_BOARDNAME "P2020RDB-PC"
146 #define CONFIG_NAND_FSL_ELBC
147 #define CONFIG_VSC7385_ENET
148 #define __SW_BOOT_MASK 0x03
149 #define __SW_BOOT_NOR 0xc8
150 #define __SW_BOOT_SPI 0x28
151 #define __SW_BOOT_SD 0x68 /* or 0x18 */
152 #define __SW_BOOT_NAND 0xe8
153 #define __SW_BOOT_PCIE 0xa8
154 #define CONFIG_SYS_L2_SIZE (512 << 10)
156 * Dynamic MTD Partition support with mtdparts
158 #define CONFIG_MTD_DEVICE
159 #define CONFIG_MTD_PARTITIONS
160 #define CONFIG_CMD_MTDPARTS
161 #define CONFIG_FLASH_CFI_MTD
162 #ifdef CONFIG_PHYS_64BIT
163 #define MTDIDS_DEFAULT "nor0=fef000000.nor"
164 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
165 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
167 #define MTDIDS_DEFAULT "nor0=ef000000.nor"
168 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
169 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
174 #define CONFIG_SPL_MMC_MINIMAL
175 #define CONFIG_SPL_FLUSH_IMAGE
176 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
177 #define CONFIG_SYS_TEXT_BASE 0x11001000
178 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
179 #define CONFIG_SPL_PAD_TO 0x20000
180 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
181 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
182 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
183 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
184 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
185 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
186 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
187 #define CONFIG_SPL_MMC_BOOT
188 #ifdef CONFIG_SPL_BUILD
189 #define CONFIG_SPL_COMMON_INIT_DDR
193 #ifdef CONFIG_SPIFLASH
194 #define CONFIG_SPL_SPI_FLASH_MINIMAL
195 #define CONFIG_SPL_FLUSH_IMAGE
196 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
197 #define CONFIG_SYS_TEXT_BASE 0x11001000
198 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
199 #define CONFIG_SPL_PAD_TO 0x20000
200 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
201 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
202 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
203 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
204 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
205 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
206 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
207 #define CONFIG_SPL_SPI_BOOT
208 #ifdef CONFIG_SPL_BUILD
209 #define CONFIG_SPL_COMMON_INIT_DDR
214 #ifdef CONFIG_TPL_BUILD
215 #define CONFIG_SPL_NAND_BOOT
216 #define CONFIG_SPL_FLUSH_IMAGE
217 #define CONFIG_SPL_NAND_INIT
218 #define CONFIG_SPL_COMMON_INIT_DDR
219 #define CONFIG_SPL_MAX_SIZE (128 << 10)
220 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
221 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
222 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
223 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
224 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
225 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
226 #elif defined(CONFIG_SPL_BUILD)
227 #define CONFIG_SPL_INIT_MINIMAL
228 #define CONFIG_SPL_FLUSH_IMAGE
229 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
230 #define CONFIG_SPL_TEXT_BASE 0xff800000
231 #define CONFIG_SPL_MAX_SIZE 4096
232 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
233 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
234 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
235 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
236 #endif /* not CONFIG_TPL_BUILD */
238 #define CONFIG_SPL_PAD_TO 0x20000
239 #define CONFIG_TPL_PAD_TO 0x20000
240 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
241 #define CONFIG_SYS_TEXT_BASE 0x11001000
242 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
245 #ifndef CONFIG_SYS_TEXT_BASE
246 #define CONFIG_SYS_TEXT_BASE 0xeff40000
249 #ifndef CONFIG_RESET_VECTOR_ADDRESS
250 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
253 #ifndef CONFIG_SYS_MONITOR_BASE
254 #ifdef CONFIG_SPL_BUILD
255 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
257 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
263 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
264 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
265 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
266 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
267 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
268 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
270 #define CONFIG_TSEC_ENET /* tsec ethernet support */
271 #define CONFIG_ENV_OVERWRITE
273 #define CONFIG_CMD_SATA
274 #define CONFIG_SATA_SIL
275 #define CONFIG_SYS_SATA_MAX_DEVICE 2
276 #define CONFIG_LIBATA
279 #if defined(CONFIG_TARGET_P2020RDB)
280 #define CONFIG_SYS_CLK_FREQ 100000000
282 #define CONFIG_SYS_CLK_FREQ 66666666
284 #define CONFIG_DDR_CLK_FREQ 66666666
286 #define CONFIG_HWCONFIG
288 * These can be toggled for performance analysis, otherwise use default.
290 #define CONFIG_L2_CACHE
293 #define CONFIG_ENABLE_36BIT_PHYS
295 #ifdef CONFIG_PHYS_64BIT
296 #define CONFIG_ADDR_MAP 1
297 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
300 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
301 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
302 #define CONFIG_PANIC_HANG /* do not reset board on panic */
304 #define CONFIG_SYS_CCSRBAR 0xffe00000
305 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
307 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
309 #ifdef CONFIG_SPL_BUILD
310 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
314 #define CONFIG_SYS_DDR_RAW_TIMING
315 #define CONFIG_DDR_SPD
316 #define CONFIG_SYS_SPD_BUS_NUM 1
317 #define SPD_EEPROM_ADDRESS 0x52
318 #undef CONFIG_FSL_DDR_INTERACTIVE
320 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
321 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
322 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
324 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
325 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
327 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
328 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
329 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
331 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
333 /* Default settings for DDR3 */
334 #ifndef CONFIG_TARGET_P2020RDB
335 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
336 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
337 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
338 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
339 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
340 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
342 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
343 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
344 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
345 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
347 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
348 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
349 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
350 #define CONFIG_SYS_DDR_RCW_1 0x00000000
351 #define CONFIG_SYS_DDR_RCW_2 0x00000000
352 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
353 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
354 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
355 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
357 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
358 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
359 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
360 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
361 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
362 #define CONFIG_SYS_DDR_MODE_1 0x40461520
363 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
364 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
367 #undef CONFIG_CLOCKS_IN_MHZ
372 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
373 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
374 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
375 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
377 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
378 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
379 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
380 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
381 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
382 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
383 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
387 * Local Bus Definitions
389 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
390 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
391 #define CONFIG_SYS_FLASH_BASE 0xec000000
392 #elif defined(CONFIG_TARGET_P1020UTM)
393 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
394 #define CONFIG_SYS_FLASH_BASE 0xee000000
396 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
397 #define CONFIG_SYS_FLASH_BASE 0xef000000
400 #ifdef CONFIG_PHYS_64BIT
401 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
403 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
406 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
409 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
411 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
412 #define CONFIG_SYS_FLASH_QUIET_TEST
413 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
415 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
417 #undef CONFIG_SYS_FLASH_CHECKSUM
418 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
419 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
421 #define CONFIG_FLASH_CFI_DRIVER
422 #define CONFIG_SYS_FLASH_CFI
423 #define CONFIG_SYS_FLASH_EMPTY_INFO
424 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
427 #ifdef CONFIG_NAND_FSL_ELBC
428 #define CONFIG_SYS_NAND_BASE 0xff800000
429 #ifdef CONFIG_PHYS_64BIT
430 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
432 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
435 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
436 #define CONFIG_SYS_MAX_NAND_DEVICE 1
437 #define CONFIG_CMD_NAND
438 #if defined(CONFIG_TARGET_P1020RDB_PD)
439 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
441 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
444 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
445 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
446 | BR_PS_8 /* Port Size = 8 bit */ \
447 | BR_MS_FCM /* MSEL = FCM */ \
449 #if defined(CONFIG_TARGET_P1020RDB_PD)
450 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
451 | OR_FCM_PGS /* Large Page*/ \
459 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
467 #endif /* CONFIG_NAND_FSL_ELBC */
469 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
471 #define CONFIG_SYS_INIT_RAM_LOCK
472 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
473 #ifdef CONFIG_PHYS_64BIT
474 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
475 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
476 /* The assembler doesn't like typecast */
477 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
478 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
479 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
481 /* Initial L1 address */
482 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
483 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
484 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
486 /* Size of used area in RAM */
487 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
489 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
490 GENERATED_GBL_DATA_SIZE)
491 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
493 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
494 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
496 #define CONFIG_SYS_CPLD_BASE 0xffa00000
497 #ifdef CONFIG_PHYS_64BIT
498 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
500 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
502 /* CPLD config size: 1Mb */
503 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
505 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
507 #define CONFIG_SYS_PMC_BASE 0xff980000
508 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
509 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
511 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
512 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
516 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
517 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
518 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
519 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
521 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
522 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
523 #ifdef CONFIG_NAND_FSL_ELBC
524 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
525 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
528 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
529 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
532 #ifdef CONFIG_VSC7385_ENET
533 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
535 #ifdef CONFIG_PHYS_64BIT
536 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
538 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
541 #define CONFIG_SYS_VSC7385_BR_PRELIM \
542 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
543 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
544 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
545 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
547 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
548 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
550 /* The size of the VSC7385 firmware image */
551 #define CONFIG_VSC7385_IMAGE_SIZE 8192
555 * Config the L2 Cache as L2 SRAM
557 #if defined(CONFIG_SPL_BUILD)
558 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
559 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
560 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
561 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
562 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
563 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
564 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
565 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
566 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
567 #if defined(CONFIG_TARGET_P2020RDB)
568 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
570 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
572 #elif defined(CONFIG_NAND)
573 #ifdef CONFIG_TPL_BUILD
574 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
575 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
576 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
577 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
578 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
579 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
580 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
581 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
583 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
584 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
585 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
586 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
587 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
588 #endif /* CONFIG_TPL_BUILD */
592 /* Serial Port - controlled on board with jumper J8
596 #define CONFIG_CONS_INDEX 1
597 #undef CONFIG_SERIAL_SOFTWARE_FIFO
598 #define CONFIG_SYS_NS16550_SERIAL
599 #define CONFIG_SYS_NS16550_REG_SIZE 1
600 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
601 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
602 #define CONFIG_NS16550_MIN_FUNCTIONS
605 #define CONFIG_SYS_BAUDRATE_TABLE \
606 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
608 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
609 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
612 #define CONFIG_SYS_I2C
613 #define CONFIG_SYS_I2C_FSL
614 #define CONFIG_SYS_FSL_I2C_SPEED 400000
615 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
616 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
617 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
618 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
619 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
620 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
621 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
622 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
627 #undef CONFIG_ID_EEPROM
629 #define CONFIG_RTC_PT7C4338
630 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
631 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
633 /* enable read and write access to EEPROM */
634 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
635 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
636 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
639 * eSPI - Enhanced SPI
641 #define CONFIG_HARD_SPI
643 #if defined(CONFIG_SPI_FLASH)
644 #define CONFIG_SF_DEFAULT_SPEED 10000000
645 #define CONFIG_SF_DEFAULT_MODE 0
648 #if defined(CONFIG_PCI)
651 * Memory space is mapped 1-1, but I/O space must start from 0.
654 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
655 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
656 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
657 #ifdef CONFIG_PHYS_64BIT
658 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
659 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
661 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
662 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
664 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
665 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
666 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
667 #ifdef CONFIG_PHYS_64BIT
668 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
670 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
672 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
674 /* controller 1, Slot 2, tgtid 1, Base address a000 */
675 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
676 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
677 #ifdef CONFIG_PHYS_64BIT
678 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
679 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
681 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
682 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
684 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
685 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
686 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
687 #ifdef CONFIG_PHYS_64BIT
688 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
690 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
692 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
694 #define CONFIG_CMD_PCI
696 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
697 #endif /* CONFIG_PCI */
699 #if defined(CONFIG_TSEC_ENET)
700 #define CONFIG_MII /* MII PHY management */
702 #define CONFIG_TSEC1_NAME "eTSEC1"
704 #define CONFIG_TSEC2_NAME "eTSEC2"
706 #define CONFIG_TSEC3_NAME "eTSEC3"
708 #define TSEC1_PHY_ADDR 2
709 #define TSEC2_PHY_ADDR 0
710 #define TSEC3_PHY_ADDR 1
712 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
713 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
714 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
716 #define TSEC1_PHYIDX 0
717 #define TSEC2_PHYIDX 0
718 #define TSEC3_PHYIDX 0
720 #define CONFIG_ETHPRIME "eTSEC1"
722 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
724 #define CONFIG_HAS_ETH0
725 #define CONFIG_HAS_ETH1
726 #define CONFIG_HAS_ETH2
727 #endif /* CONFIG_TSEC_ENET */
730 /* QE microcode/firmware address */
731 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
732 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
733 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
734 #endif /* CONFIG_QE */
736 #ifdef CONFIG_TARGET_P1025RDB
738 * QE UEC ethernet configuration
740 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
742 #undef CONFIG_UEC_ETH
743 #define CONFIG_PHY_MODE_NEED_CHANGE
745 #define CONFIG_UEC_ETH1 /* ETH1 */
746 #define CONFIG_HAS_ETH0
748 #ifdef CONFIG_UEC_ETH1
749 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
750 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
751 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
752 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
753 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
754 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
755 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
756 #endif /* CONFIG_UEC_ETH1 */
758 #define CONFIG_UEC_ETH5 /* ETH5 */
759 #define CONFIG_HAS_ETH1
761 #ifdef CONFIG_UEC_ETH5
762 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
763 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
764 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
765 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
766 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
767 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
768 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
769 #endif /* CONFIG_UEC_ETH5 */
770 #endif /* CONFIG_TARGET_P1025RDB */
775 #ifdef CONFIG_SPIFLASH
776 #define CONFIG_ENV_IS_IN_SPI_FLASH
777 #define CONFIG_ENV_SPI_BUS 0
778 #define CONFIG_ENV_SPI_CS 0
779 #define CONFIG_ENV_SPI_MAX_HZ 10000000
780 #define CONFIG_ENV_SPI_MODE 0
781 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
782 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
783 #define CONFIG_ENV_SECT_SIZE 0x10000
784 #elif defined(CONFIG_SDCARD)
785 #define CONFIG_ENV_IS_IN_MMC
786 #define CONFIG_FSL_FIXED_MMC_LOCATION
787 #define CONFIG_ENV_SIZE 0x2000
788 #define CONFIG_SYS_MMC_ENV_DEV 0
789 #elif defined(CONFIG_NAND)
790 #ifdef CONFIG_TPL_BUILD
791 #define CONFIG_ENV_SIZE 0x2000
792 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
794 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
796 #define CONFIG_ENV_IS_IN_NAND
797 #define CONFIG_ENV_OFFSET (1024 * 1024)
798 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
799 #elif defined(CONFIG_SYS_RAMBOOT)
800 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
801 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
802 #define CONFIG_ENV_SIZE 0x2000
804 #define CONFIG_ENV_IS_IN_FLASH
805 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
806 #define CONFIG_ENV_SIZE 0x2000
807 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
810 #define CONFIG_LOADS_ECHO /* echo on for serial download */
811 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
814 * Command line configuration.
816 #define CONFIG_CMD_REGINFO
821 #define CONFIG_HAS_FSL_DR_USB
823 #if defined(CONFIG_HAS_FSL_DR_USB)
824 #ifdef CONFIG_USB_EHCI_HCD
825 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
826 #define CONFIG_USB_EHCI_FSL
830 #if defined(CONFIG_TARGET_P1020RDB_PD)
831 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
835 #define CONFIG_FSL_ESDHC
836 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
839 #undef CONFIG_WATCHDOG /* watchdog disabled */
842 * Miscellaneous configurable options
844 #define CONFIG_SYS_LONGHELP /* undef to save memory */
845 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
846 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
847 #if defined(CONFIG_CMD_KGDB)
848 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
850 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
852 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
853 /* Print Buffer Size */
854 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
855 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
858 * For booting Linux, the board info and command line data
859 * have to be in the first 64 MB of memory, since this is
860 * the maximum mapped by the Linux kernel during initialization.
862 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
863 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
865 #if defined(CONFIG_CMD_KGDB)
866 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
870 * Environment Configuration
872 #define CONFIG_HOSTNAME unknown
873 #define CONFIG_ROOTPATH "/opt/nfsroot"
874 #define CONFIG_BOOTFILE "uImage"
875 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
877 /* default location for tftp and bootm */
878 #define CONFIG_LOADADDR 1000000
880 #define CONFIG_BOOTARGS /* the boot command will set bootargs */
883 #define __NOR_RST_CMD \
884 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
885 i2c mw 18 3 __SW_BOOT_MASK 1; reset
888 #define __SPI_RST_CMD \
889 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
890 i2c mw 18 3 __SW_BOOT_MASK 1; reset
893 #define __SD_RST_CMD \
894 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
895 i2c mw 18 3 __SW_BOOT_MASK 1; reset
897 #ifdef __SW_BOOT_NAND
898 #define __NAND_RST_CMD \
899 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
900 i2c mw 18 3 __SW_BOOT_MASK 1; reset
902 #ifdef __SW_BOOT_PCIE
903 #define __PCIE_RST_CMD \
904 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
905 i2c mw 18 3 __SW_BOOT_MASK 1; reset
908 #define CONFIG_EXTRA_ENV_SETTINGS \
910 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
911 "loadaddr=1000000\0" \
912 "bootfile=uImage\0" \
913 "tftpflash=tftpboot $loadaddr $uboot; " \
914 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
915 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
916 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
917 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
918 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
919 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
920 "consoledev=ttyS0\0" \
921 "ramdiskaddr=2000000\0" \
922 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
923 "fdtaddr=1e00000\0" \
925 "jffs2nor=mtdblock3\0" \
926 "norbootaddr=ef080000\0" \
927 "norfdtaddr=ef040000\0" \
928 "jffs2nand=mtdblock9\0" \
929 "nandbootaddr=100000\0" \
930 "nandfdtaddr=80000\0" \
931 "ramdisk_size=120000\0" \
932 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
933 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
934 __stringify(__NOR_RST_CMD)"\0" \
935 __stringify(__SPI_RST_CMD)"\0" \
936 __stringify(__SD_RST_CMD)"\0" \
937 __stringify(__NAND_RST_CMD)"\0" \
938 __stringify(__PCIE_RST_CMD)"\0"
940 #define CONFIG_NFSBOOTCOMMAND \
941 "setenv bootargs root=/dev/nfs rw " \
942 "nfsroot=$serverip:$rootpath " \
943 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
944 "console=$consoledev,$baudrate $othbootargs;" \
945 "tftp $loadaddr $bootfile;" \
946 "tftp $fdtaddr $fdtfile;" \
947 "bootm $loadaddr - $fdtaddr"
949 #define CONFIG_HDBOOT \
950 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
951 "console=$consoledev,$baudrate $othbootargs;" \
953 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
954 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
955 "bootm $loadaddr - $fdtaddr"
957 #define CONFIG_USB_FAT_BOOT \
958 "setenv bootargs root=/dev/ram rw " \
959 "console=$consoledev,$baudrate $othbootargs " \
960 "ramdisk_size=$ramdisk_size;" \
962 "fatload usb 0:2 $loadaddr $bootfile;" \
963 "fatload usb 0:2 $fdtaddr $fdtfile;" \
964 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
965 "bootm $loadaddr $ramdiskaddr $fdtaddr"
967 #define CONFIG_USB_EXT2_BOOT \
968 "setenv bootargs root=/dev/ram rw " \
969 "console=$consoledev,$baudrate $othbootargs " \
970 "ramdisk_size=$ramdisk_size;" \
972 "ext2load usb 0:4 $loadaddr $bootfile;" \
973 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
974 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
975 "bootm $loadaddr $ramdiskaddr $fdtaddr"
977 #define CONFIG_NORBOOT \
978 "setenv bootargs root=/dev/$jffs2nor rw " \
979 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
980 "bootm $norbootaddr - $norfdtaddr"
982 #define CONFIG_RAMBOOTCOMMAND \
983 "setenv bootargs root=/dev/ram rw " \
984 "console=$consoledev,$baudrate $othbootargs " \
985 "ramdisk_size=$ramdisk_size;" \
986 "tftp $ramdiskaddr $ramdiskfile;" \
987 "tftp $loadaddr $bootfile;" \
988 "tftp $fdtaddr $fdtfile;" \
989 "bootm $loadaddr $ramdiskaddr $fdtaddr"
991 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
993 #endif /* __CONFIG_H */