1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * QorIQ RDB boards configuration file
13 #include <linux/stringify.h>
15 #if defined(CONFIG_TARGET_P1020RDB_PC)
16 #define CONFIG_VSC7385_ENET
18 #define __SW_BOOT_MASK 0x03
19 #define __SW_BOOT_NOR 0x5c
20 #define __SW_BOOT_SPI 0x1c
21 #define __SW_BOOT_SD 0x9c
22 #define __SW_BOOT_NAND 0xec
23 #define __SW_BOOT_PCIE 0x6c
24 #define __SW_NOR_BANK_MASK 0xfd
25 #define __SW_NOR_BANK_UP 0x00
26 #define __SW_NOR_BANK_LO 0x02
27 #define CONFIG_SYS_L2_SIZE (256 << 10)
31 * P1020RDB-PD board has user selectable switches for evaluating different
32 * frequency and boot options for the P1020 device. The table that
33 * follow describe the available options. The front six binary number was in
34 * accordance with SW3[1:6].
35 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
36 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
37 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
38 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
39 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
40 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
41 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
43 #if defined(CONFIG_TARGET_P1020RDB_PD)
44 #define CONFIG_VSC7385_ENET
46 #define __SW_BOOT_MASK 0x03
47 #define __SW_BOOT_NOR 0x64
48 #define __SW_BOOT_SPI 0x34
49 #define __SW_BOOT_SD 0x24
50 #define __SW_BOOT_NAND 0x44
51 #define __SW_BOOT_PCIE 0x74
52 #define __SW_NOR_BANK_MASK 0xfd
53 #define __SW_NOR_BANK_UP 0x00
54 #define __SW_NOR_BANK_LO 0x02
55 #define CONFIG_SYS_L2_SIZE (256 << 10)
57 * Dynamic MTD Partition support with mtdparts
61 #if defined(CONFIG_TARGET_P2020RDB)
62 #define CONFIG_VSC7385_ENET
63 #define __SW_BOOT_MASK 0x03
64 #define __SW_BOOT_NOR 0xc8
65 #define __SW_BOOT_SPI 0x28
66 #define __SW_BOOT_SD 0x68
67 #define __SW_BOOT_SD2 0x18
68 #define __SW_BOOT_NAND 0xe8
69 #define __SW_BOOT_PCIE 0xa8
70 #define __SW_NOR_BANK_MASK 0xfd
71 #define __SW_NOR_BANK_UP 0x00
72 #define __SW_NOR_BANK_LO 0x02
73 #define CONFIG_SYS_L2_SIZE (512 << 10)
75 * Dynamic MTD Partition support with mtdparts
80 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
81 #define CONFIG_SYS_MMC_U_BOOT_DST CONFIG_SYS_TEXT_BASE
82 #define CONFIG_SYS_MMC_U_BOOT_START CONFIG_SYS_TEXT_BASE
83 #define CONFIG_SYS_MMC_U_BOOT_OFFS CONFIG_SPL_PAD_TO
84 #elif defined(CONFIG_SPIFLASH)
85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_SYS_TEXT_BASE
87 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START CONFIG_SYS_TEXT_BASE
88 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SPL_PAD_TO
89 #elif defined(CONFIG_MTD_RAW_NAND)
90 #ifdef CONFIG_TPL_BUILD
91 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
92 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
93 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
94 #elif defined(CONFIG_SPL_BUILD)
95 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
96 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
97 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
98 #endif /* not CONFIG_TPL_BUILD */
101 #ifndef CONFIG_RESET_VECTOR_ADDRESS
102 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
105 #define CONFIG_HWCONFIG
107 * These can be toggled for performance analysis, otherwise use default.
109 #define CONFIG_L2_CACHE
111 #define CONFIG_SYS_CCSRBAR 0xffe00000
112 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
115 #define SPD_EEPROM_ADDRESS 0x52
117 #if defined(CONFIG_TARGET_P1020RDB_PD)
118 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
120 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
122 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
123 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
124 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
126 /* Default settings for DDR3 */
127 #ifndef CONFIG_TARGET_P2020RDB
128 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
129 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
130 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
131 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
132 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
133 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
135 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
136 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
137 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
139 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
140 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
141 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
142 #define CONFIG_SYS_DDR_RCW_1 0x00000000
143 #define CONFIG_SYS_DDR_RCW_2 0x00000000
144 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
145 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
146 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
147 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
149 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
150 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
151 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
152 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
153 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
154 #define CONFIG_SYS_DDR_MODE_1 0x40461520
155 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
156 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
162 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
163 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
164 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
165 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
167 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
168 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
169 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
170 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
171 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
172 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
176 * Local Bus Definitions
178 #if defined(CONFIG_TARGET_P1020RDB_PD)
179 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
180 #define CONFIG_SYS_FLASH_BASE 0xec000000
182 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
183 #define CONFIG_SYS_FLASH_BASE 0xef000000
186 #ifdef CONFIG_PHYS_64BIT
187 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
189 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
192 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
195 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
197 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
198 #define CONFIG_SYS_FLASH_QUIET_TEST
199 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
201 #undef CONFIG_SYS_FLASH_CHECKSUM
202 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
203 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
206 #ifdef CONFIG_NAND_FSL_ELBC
207 #define CONFIG_SYS_NAND_BASE 0xff800000
208 #ifdef CONFIG_PHYS_64BIT
209 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
211 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
214 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
215 #define CONFIG_SYS_MAX_NAND_DEVICE 1
217 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
218 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
219 | BR_PS_8 /* Port Size = 8 bit */ \
220 | BR_MS_FCM /* MSEL = FCM */ \
222 #if defined(CONFIG_TARGET_P1020RDB_PD)
223 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
224 | OR_FCM_PGS /* Large Page*/ \
232 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
240 #endif /* CONFIG_NAND_FSL_ELBC */
242 #define CONFIG_SYS_INIT_RAM_LOCK
243 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
244 #ifdef CONFIG_PHYS_64BIT
245 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
246 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
247 /* The assembler doesn't like typecast */
248 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
249 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
250 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
252 /* Initial L1 address */
253 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
254 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
255 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
257 /* Size of used area in RAM */
258 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
260 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
262 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
264 #define CONFIG_SYS_CPLD_BASE 0xffa00000
265 #ifdef CONFIG_PHYS_64BIT
266 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
268 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
270 /* CPLD config size: 1Mb */
273 #ifdef CONFIG_VSC7385_ENET
274 #define __VSCFW_ADDR "vscfw_addr=ef000000\0"
275 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
277 #ifdef CONFIG_PHYS_64BIT
278 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
280 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
283 #define CONFIG_SYS_VSC7385_BR_PRELIM \
284 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
285 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
286 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
287 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
289 /* The size of the VSC7385 firmware image */
290 #define CONFIG_VSC7385_IMAGE_SIZE 8192
294 #define __VSCFW_ADDR ""
298 * Config the L2 Cache as L2 SRAM
300 #if defined(CONFIG_SPL_BUILD)
301 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
302 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
303 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
304 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
305 #elif defined(CONFIG_MTD_RAW_NAND)
306 #ifdef CONFIG_TPL_BUILD
307 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
308 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
309 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
311 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
312 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
313 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
314 #endif /* CONFIG_TPL_BUILD */
318 /* Serial Port - controlled on board with jumper J8
322 #undef CONFIG_SERIAL_SOFTWARE_FIFO
323 #define CONFIG_SYS_NS16550_SERIAL
324 #define CONFIG_SYS_NS16550_REG_SIZE 1
325 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
326 #if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)
327 #define CONFIG_NS16550_MIN_FUNCTIONS
330 #define CONFIG_SYS_BAUDRATE_TABLE \
331 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
333 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
334 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
337 #if !CONFIG_IS_ENABLED(DM_I2C)
338 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
345 #define CONFIG_RTC_PT7C4338
346 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
347 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
349 /* enable read and write access to EEPROM */
351 #if defined(CONFIG_PCI)
354 * Memory space is mapped 1-1, but I/O space must start from 0.
357 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
358 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
359 #ifdef CONFIG_PHYS_64BIT
360 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
362 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
364 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
365 #ifdef CONFIG_PHYS_64BIT
366 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
368 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
371 /* controller 1, Slot 2, tgtid 1, Base address a000 */
372 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
373 #ifdef CONFIG_PHYS_64BIT
374 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
376 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
378 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
379 #ifdef CONFIG_PHYS_64BIT
380 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
382 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
384 #endif /* CONFIG_PCI */
386 #if defined(CONFIG_TSEC_ENET)
388 #define CONFIG_TSEC1_NAME "eTSEC1"
390 #define CONFIG_TSEC2_NAME "eTSEC2"
392 #define CONFIG_TSEC3_NAME "eTSEC3"
394 #define TSEC1_PHY_ADDR 2
395 #define TSEC2_PHY_ADDR 0
396 #define TSEC3_PHY_ADDR 1
398 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
399 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
400 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
402 #define TSEC1_PHYIDX 0
403 #define TSEC2_PHYIDX 0
404 #define TSEC3_PHYIDX 0
405 #endif /* CONFIG_TSEC_ENET */
410 #if defined(CONFIG_MTD_RAW_NAND)
411 #ifdef CONFIG_TPL_BUILD
412 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
416 #define CONFIG_LOADS_ECHO /* echo on for serial download */
417 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
424 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
428 * Miscellaneous configurable options
432 * For booting Linux, the board info and command line data
433 * have to be in the first 64 MB of memory, since this is
434 * the maximum mapped by the Linux kernel during initialization.
436 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
439 * Environment Configuration
441 #define CONFIG_HOSTNAME "unknown"
442 #define CONFIG_ROOTPATH "/opt/nfsroot"
443 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
445 #include "p1_p2_bootsrc.h"
447 #define CONFIG_EXTRA_ENV_SETTINGS \
449 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
450 "loadaddr=1000000\0" \
451 "bootfile=uImage\0" \
452 "tftpflash=tftpboot $loadaddr $uboot; " \
453 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
454 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
455 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
456 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
457 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
458 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
459 "consoledev=ttyS0\0" \
460 "ramdiskaddr=2000000\0" \
461 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
462 "fdtaddr=1e00000\0" \
464 "jffs2nor=mtdblock3\0" \
465 "norbootaddr=ef080000\0" \
466 "norfdtaddr=ef040000\0" \
467 "jffs2nand=mtdblock9\0" \
468 "nandbootaddr=100000\0" \
469 "nandfdtaddr=80000\0" \
470 "ramdisk_size=120000\0" \
472 MAP_NOR_LO_CMD(map_lowernorbank) \
473 MAP_NOR_UP_CMD(map_uppernorbank) \
474 RST_NOR_CMD(norboot) \
475 RST_SPI_CMD(spiboot) \
477 RST_NAND_CMD(nandboot) \
478 RST_PCIE_CMD(pciboot) \
481 #define CONFIG_USB_FAT_BOOT \
482 "setenv bootargs root=/dev/ram rw " \
483 "console=$consoledev,$baudrate $othbootargs " \
484 "ramdisk_size=$ramdisk_size;" \
486 "fatload usb 0:2 $loadaddr $bootfile;" \
487 "fatload usb 0:2 $fdtaddr $fdtfile;" \
488 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
489 "bootm $loadaddr $ramdiskaddr $fdtaddr"
491 #define CONFIG_USB_EXT2_BOOT \
492 "setenv bootargs root=/dev/ram rw " \
493 "console=$consoledev,$baudrate $othbootargs " \
494 "ramdisk_size=$ramdisk_size;" \
496 "ext2load usb 0:4 $loadaddr $bootfile;" \
497 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
498 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
499 "bootm $loadaddr $ramdiskaddr $fdtaddr"
501 #define CONFIG_NORBOOT \
502 "setenv bootargs root=/dev/$jffs2nor rw " \
503 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
504 "bootm $norbootaddr - $norfdtaddr"
506 #endif /* __CONFIG_H */