2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * QorIQ RDB boards configuration file
13 #if defined(CONFIG_TARGET_P1020MBG)
14 #define CONFIG_BOARDNAME "P1020MBG-PC"
15 #define CONFIG_VSC7385_ENET
17 #define __SW_BOOT_MASK 0x03
18 #define __SW_BOOT_NOR 0xe4
19 #define __SW_BOOT_SD 0x54
20 #define CONFIG_SYS_L2_SIZE (256 << 10)
23 #if defined(CONFIG_TARGET_P1020UTM)
24 #define CONFIG_BOARDNAME "P1020UTM-PC"
25 #define __SW_BOOT_MASK 0x03
26 #define __SW_BOOT_NOR 0xe0
27 #define __SW_BOOT_SD 0x50
28 #define CONFIG_SYS_L2_SIZE (256 << 10)
31 #if defined(CONFIG_TARGET_P1020RDB_PC)
32 #define CONFIG_BOARDNAME "P1020RDB-PC"
33 #define CONFIG_NAND_FSL_ELBC
34 #define CONFIG_VSC7385_ENET
36 #define __SW_BOOT_MASK 0x03
37 #define __SW_BOOT_NOR 0x5c
38 #define __SW_BOOT_SPI 0x1c
39 #define __SW_BOOT_SD 0x9c
40 #define __SW_BOOT_NAND 0xec
41 #define __SW_BOOT_PCIE 0x6c
42 #define CONFIG_SYS_L2_SIZE (256 << 10)
46 * P1020RDB-PD board has user selectable switches for evaluating different
47 * frequency and boot options for the P1020 device. The table that
48 * follow describe the available options. The front six binary number was in
49 * accordance with SW3[1:6].
50 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
51 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
52 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
53 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
54 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
55 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
56 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
58 #if defined(CONFIG_TARGET_P1020RDB_PD)
59 #define CONFIG_BOARDNAME "P1020RDB-PD"
60 #define CONFIG_NAND_FSL_ELBC
61 #define CONFIG_VSC7385_ENET
63 #define __SW_BOOT_MASK 0x03
64 #define __SW_BOOT_NOR 0x64
65 #define __SW_BOOT_SPI 0x34
66 #define __SW_BOOT_SD 0x24
67 #define __SW_BOOT_NAND 0x44
68 #define __SW_BOOT_PCIE 0x74
69 #define CONFIG_SYS_L2_SIZE (256 << 10)
71 * Dynamic MTD Partition support with mtdparts
73 #define CONFIG_MTD_DEVICE
74 #define CONFIG_MTD_PARTITIONS
75 #define CONFIG_CMD_MTDPARTS
76 #define CONFIG_FLASH_CFI_MTD
77 #define MTDIDS_DEFAULT "nor0=ec000000.nor"
78 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \
79 "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
82 #if defined(CONFIG_TARGET_P1021RDB)
83 #define CONFIG_BOARDNAME "P1021RDB-PC"
84 #define CONFIG_NAND_FSL_ELBC
86 #define CONFIG_VSC7385_ENET
87 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
88 addresses in the LBC */
89 #define __SW_BOOT_MASK 0x03
90 #define __SW_BOOT_NOR 0x5c
91 #define __SW_BOOT_SPI 0x1c
92 #define __SW_BOOT_SD 0x9c
93 #define __SW_BOOT_NAND 0xec
94 #define __SW_BOOT_PCIE 0x6c
95 #define CONFIG_SYS_L2_SIZE (256 << 10)
97 * Dynamic MTD Partition support with mtdparts
99 #define CONFIG_MTD_DEVICE
100 #define CONFIG_MTD_PARTITIONS
101 #define CONFIG_CMD_MTDPARTS
102 #define CONFIG_FLASH_CFI_MTD
103 #ifdef CONFIG_PHYS_64BIT
104 #define MTDIDS_DEFAULT "nor0=fef000000.nor"
105 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
106 "256k(dtb),4608k(kernel),9728k(fs)," \
107 "256k(qe-ucode-firmware),1280k(u-boot)"
109 #define MTDIDS_DEFAULT "nor0=ef000000.nor"
110 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
111 "256k(dtb),4608k(kernel),9728k(fs)," \
112 "256k(qe-ucode-firmware),1280k(u-boot)"
116 #if defined(CONFIG_TARGET_P1024RDB)
117 #define CONFIG_BOARDNAME "P1024RDB"
118 #define CONFIG_NAND_FSL_ELBC
121 #define __SW_BOOT_MASK 0xf3
122 #define __SW_BOOT_NOR 0x00
123 #define __SW_BOOT_SPI 0x08
124 #define __SW_BOOT_SD 0x04
125 #define __SW_BOOT_NAND 0x0c
126 #define CONFIG_SYS_L2_SIZE (256 << 10)
129 #if defined(CONFIG_TARGET_P1025RDB)
130 #define CONFIG_BOARDNAME "P1025RDB"
131 #define CONFIG_NAND_FSL_ELBC
136 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
137 addresses in the LBC */
138 #define __SW_BOOT_MASK 0xf3
139 #define __SW_BOOT_NOR 0x00
140 #define __SW_BOOT_SPI 0x08
141 #define __SW_BOOT_SD 0x04
142 #define __SW_BOOT_NAND 0x0c
143 #define CONFIG_SYS_L2_SIZE (256 << 10)
146 #if defined(CONFIG_TARGET_P2020RDB)
147 #define CONFIG_BOARDNAME "P2020RDB-PC"
148 #define CONFIG_NAND_FSL_ELBC
150 #define CONFIG_VSC7385_ENET
151 #define __SW_BOOT_MASK 0x03
152 #define __SW_BOOT_NOR 0xc8
153 #define __SW_BOOT_SPI 0x28
154 #define __SW_BOOT_SD 0x68 /* or 0x18 */
155 #define __SW_BOOT_NAND 0xe8
156 #define __SW_BOOT_PCIE 0xa8
157 #define CONFIG_SYS_L2_SIZE (512 << 10)
159 * Dynamic MTD Partition support with mtdparts
161 #define CONFIG_MTD_DEVICE
162 #define CONFIG_MTD_PARTITIONS
163 #define CONFIG_CMD_MTDPARTS
164 #define CONFIG_FLASH_CFI_MTD
165 #ifdef CONFIG_PHYS_64BIT
166 #define MTDIDS_DEFAULT "nor0=fef000000.nor"
167 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
168 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
170 #define MTDIDS_DEFAULT "nor0=ef000000.nor"
171 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
172 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
177 #define CONFIG_SPL_MMC_MINIMAL
178 #define CONFIG_SPL_FLUSH_IMAGE
179 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
180 #define CONFIG_FSL_LAW /* Use common FSL init code */
181 #define CONFIG_SYS_TEXT_BASE 0x11001000
182 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
183 #define CONFIG_SPL_PAD_TO 0x20000
184 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
185 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
186 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
187 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
188 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
189 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
190 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
191 #define CONFIG_SPL_MMC_BOOT
192 #ifdef CONFIG_SPL_BUILD
193 #define CONFIG_SPL_COMMON_INIT_DDR
197 #ifdef CONFIG_SPIFLASH
198 #define CONFIG_SPL_SPI_FLASH_MINIMAL
199 #define CONFIG_SPL_FLUSH_IMAGE
200 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
201 #define CONFIG_FSL_LAW /* Use common FSL init code */
202 #define CONFIG_SYS_TEXT_BASE 0x11001000
203 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
204 #define CONFIG_SPL_PAD_TO 0x20000
205 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
206 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
207 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
208 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
209 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
210 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
211 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
212 #define CONFIG_SPL_SPI_BOOT
213 #ifdef CONFIG_SPL_BUILD
214 #define CONFIG_SPL_COMMON_INIT_DDR
219 #ifdef CONFIG_TPL_BUILD
220 #define CONFIG_SPL_NAND_BOOT
221 #define CONFIG_SPL_FLUSH_IMAGE
222 #define CONFIG_SPL_NAND_INIT
223 #define CONFIG_SPL_COMMON_INIT_DDR
224 #define CONFIG_SPL_MAX_SIZE (128 << 10)
225 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
226 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
227 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
228 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
229 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
230 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
231 #elif defined(CONFIG_SPL_BUILD)
232 #define CONFIG_SPL_INIT_MINIMAL
233 #define CONFIG_SPL_FLUSH_IMAGE
234 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
235 #define CONFIG_SPL_TEXT_BASE 0xff800000
236 #define CONFIG_SPL_MAX_SIZE 4096
237 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
238 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
239 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
240 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
241 #endif /* not CONFIG_TPL_BUILD */
243 #define CONFIG_SPL_PAD_TO 0x20000
244 #define CONFIG_TPL_PAD_TO 0x20000
245 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
246 #define CONFIG_SYS_TEXT_BASE 0x11001000
247 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
250 #ifndef CONFIG_SYS_TEXT_BASE
251 #define CONFIG_SYS_TEXT_BASE 0xeff40000
254 #ifndef CONFIG_RESET_VECTOR_ADDRESS
255 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
258 #ifndef CONFIG_SYS_MONITOR_BASE
259 #ifdef CONFIG_SPL_BUILD
260 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
262 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
266 /* High Level Configuration Options */
272 #define CONFIG_FSL_ELBC
273 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
274 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
275 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
276 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
277 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
278 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
280 #define CONFIG_FSL_LAW
281 #define CONFIG_TSEC_ENET /* tsec ethernet support */
282 #define CONFIG_ENV_OVERWRITE
284 #define CONFIG_CMD_SATA
285 #define CONFIG_SATA_SIL
286 #define CONFIG_SYS_SATA_MAX_DEVICE 2
287 #define CONFIG_LIBATA
290 #if defined(CONFIG_TARGET_P2020RDB)
291 #define CONFIG_SYS_CLK_FREQ 100000000
293 #define CONFIG_SYS_CLK_FREQ 66666666
295 #define CONFIG_DDR_CLK_FREQ 66666666
297 #define CONFIG_HWCONFIG
299 * These can be toggled for performance analysis, otherwise use default.
301 #define CONFIG_L2_CACHE
304 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
306 #define CONFIG_ENABLE_36BIT_PHYS
308 #ifdef CONFIG_PHYS_64BIT
309 #define CONFIG_ADDR_MAP 1
310 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
313 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
314 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
315 #define CONFIG_PANIC_HANG /* do not reset board on panic */
317 #define CONFIG_SYS_CCSRBAR 0xffe00000
318 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
320 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
322 #ifdef CONFIG_SPL_BUILD
323 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
327 #define CONFIG_SYS_FSL_DDR3
328 #define CONFIG_SYS_DDR_RAW_TIMING
329 #define CONFIG_DDR_SPD
330 #define CONFIG_SYS_SPD_BUS_NUM 1
331 #define SPD_EEPROM_ADDRESS 0x52
332 #undef CONFIG_FSL_DDR_INTERACTIVE
334 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
335 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
336 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
338 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
339 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
341 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
342 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
343 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
345 #define CONFIG_NUM_DDR_CONTROLLERS 1
346 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
348 /* Default settings for DDR3 */
349 #ifndef CONFIG_TARGET_P2020RDB
350 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
351 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
352 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
353 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
354 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
355 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
357 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
358 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
359 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
360 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
362 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
363 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
364 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
365 #define CONFIG_SYS_DDR_RCW_1 0x00000000
366 #define CONFIG_SYS_DDR_RCW_2 0x00000000
367 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
368 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
369 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
370 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
372 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
373 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
374 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
375 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
376 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
377 #define CONFIG_SYS_DDR_MODE_1 0x40461520
378 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
379 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
382 #undef CONFIG_CLOCKS_IN_MHZ
387 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
388 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
389 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
390 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
392 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
393 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
394 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
395 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
396 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
397 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
398 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
402 * Local Bus Definitions
404 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
405 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
406 #define CONFIG_SYS_FLASH_BASE 0xec000000
407 #elif defined(CONFIG_TARGET_P1020UTM)
408 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
409 #define CONFIG_SYS_FLASH_BASE 0xee000000
411 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
412 #define CONFIG_SYS_FLASH_BASE 0xef000000
415 #ifdef CONFIG_PHYS_64BIT
416 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
418 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
421 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
424 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
426 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
427 #define CONFIG_SYS_FLASH_QUIET_TEST
428 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
430 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
432 #undef CONFIG_SYS_FLASH_CHECKSUM
433 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
434 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
436 #define CONFIG_FLASH_CFI_DRIVER
437 #define CONFIG_SYS_FLASH_CFI
438 #define CONFIG_SYS_FLASH_EMPTY_INFO
439 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
442 #ifdef CONFIG_NAND_FSL_ELBC
443 #define CONFIG_SYS_NAND_BASE 0xff800000
444 #ifdef CONFIG_PHYS_64BIT
445 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
447 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
450 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
451 #define CONFIG_SYS_MAX_NAND_DEVICE 1
452 #define CONFIG_CMD_NAND
453 #if defined(CONFIG_TARGET_P1020RDB_PD)
454 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
456 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
459 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
460 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
461 | BR_PS_8 /* Port Size = 8 bit */ \
462 | BR_MS_FCM /* MSEL = FCM */ \
464 #if defined(CONFIG_TARGET_P1020RDB_PD)
465 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
466 | OR_FCM_PGS /* Large Page*/ \
474 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
482 #endif /* CONFIG_NAND_FSL_ELBC */
484 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
486 #define CONFIG_SYS_INIT_RAM_LOCK
487 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
488 #ifdef CONFIG_PHYS_64BIT
489 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
490 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
491 /* The assembler doesn't like typecast */
492 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
493 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
494 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
496 /* Initial L1 address */
497 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
498 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
499 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
501 /* Size of used area in RAM */
502 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
504 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
505 GENERATED_GBL_DATA_SIZE)
506 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
508 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
509 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
511 #define CONFIG_SYS_CPLD_BASE 0xffa00000
512 #ifdef CONFIG_PHYS_64BIT
513 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
515 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
517 /* CPLD config size: 1Mb */
518 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
520 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
522 #define CONFIG_SYS_PMC_BASE 0xff980000
523 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
524 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
526 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
527 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
531 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
532 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
533 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
534 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
536 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
537 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
538 #ifdef CONFIG_NAND_FSL_ELBC
539 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
540 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
543 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
544 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
547 #ifdef CONFIG_VSC7385_ENET
548 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
550 #ifdef CONFIG_PHYS_64BIT
551 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
553 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
556 #define CONFIG_SYS_VSC7385_BR_PRELIM \
557 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
558 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
559 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
560 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
562 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
563 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
565 /* The size of the VSC7385 firmware image */
566 #define CONFIG_VSC7385_IMAGE_SIZE 8192
570 * Config the L2 Cache as L2 SRAM
572 #if defined(CONFIG_SPL_BUILD)
573 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
574 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
575 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
576 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
577 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
578 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
579 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
580 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
581 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
582 #if defined(CONFIG_TARGET_P2020RDB)
583 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
585 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
587 #elif defined(CONFIG_NAND)
588 #ifdef CONFIG_TPL_BUILD
589 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
590 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
591 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
592 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
593 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
594 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
595 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
596 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
598 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
599 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
600 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
601 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
602 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
603 #endif /* CONFIG_TPL_BUILD */
607 /* Serial Port - controlled on board with jumper J8
611 #define CONFIG_CONS_INDEX 1
612 #undef CONFIG_SERIAL_SOFTWARE_FIFO
613 #define CONFIG_SYS_NS16550_SERIAL
614 #define CONFIG_SYS_NS16550_REG_SIZE 1
615 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
616 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
617 #define CONFIG_NS16550_MIN_FUNCTIONS
620 #define CONFIG_SYS_BAUDRATE_TABLE \
621 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
623 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
624 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
627 #define CONFIG_SYS_I2C
628 #define CONFIG_SYS_I2C_FSL
629 #define CONFIG_SYS_FSL_I2C_SPEED 400000
630 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
631 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
632 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
633 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
634 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
635 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
636 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
637 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
642 #undef CONFIG_ID_EEPROM
644 #define CONFIG_RTC_PT7C4338
645 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
646 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
648 /* enable read and write access to EEPROM */
649 #define CONFIG_CMD_EEPROM
650 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
651 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
652 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
655 * eSPI - Enhanced SPI
657 #define CONFIG_HARD_SPI
659 #if defined(CONFIG_SPI_FLASH)
660 #define CONFIG_SF_DEFAULT_SPEED 10000000
661 #define CONFIG_SF_DEFAULT_MODE 0
664 #if defined(CONFIG_PCI)
667 * Memory space is mapped 1-1, but I/O space must start from 0.
670 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
671 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
672 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
673 #ifdef CONFIG_PHYS_64BIT
674 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
675 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
677 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
678 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
680 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
681 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
682 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
683 #ifdef CONFIG_PHYS_64BIT
684 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
686 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
688 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
690 /* controller 1, Slot 2, tgtid 1, Base address a000 */
691 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
692 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
693 #ifdef CONFIG_PHYS_64BIT
694 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
695 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
697 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
698 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
700 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
701 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
702 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
703 #ifdef CONFIG_PHYS_64BIT
704 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
706 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
708 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
710 #define CONFIG_CMD_PCI
712 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
713 #define CONFIG_DOS_PARTITION
714 #endif /* CONFIG_PCI */
716 #if defined(CONFIG_TSEC_ENET)
717 #define CONFIG_MII /* MII PHY management */
719 #define CONFIG_TSEC1_NAME "eTSEC1"
721 #define CONFIG_TSEC2_NAME "eTSEC2"
723 #define CONFIG_TSEC3_NAME "eTSEC3"
725 #define TSEC1_PHY_ADDR 2
726 #define TSEC2_PHY_ADDR 0
727 #define TSEC3_PHY_ADDR 1
729 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
730 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
731 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
733 #define TSEC1_PHYIDX 0
734 #define TSEC2_PHYIDX 0
735 #define TSEC3_PHYIDX 0
737 #define CONFIG_ETHPRIME "eTSEC1"
739 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
741 #define CONFIG_HAS_ETH0
742 #define CONFIG_HAS_ETH1
743 #define CONFIG_HAS_ETH2
744 #endif /* CONFIG_TSEC_ENET */
747 /* QE microcode/firmware address */
748 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
749 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
750 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
751 #endif /* CONFIG_QE */
753 #ifdef CONFIG_TARGET_P1025RDB
755 * QE UEC ethernet configuration
757 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
759 #undef CONFIG_UEC_ETH
760 #define CONFIG_PHY_MODE_NEED_CHANGE
762 #define CONFIG_UEC_ETH1 /* ETH1 */
763 #define CONFIG_HAS_ETH0
765 #ifdef CONFIG_UEC_ETH1
766 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
767 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
768 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
769 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
770 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
771 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
772 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
773 #endif /* CONFIG_UEC_ETH1 */
775 #define CONFIG_UEC_ETH5 /* ETH5 */
776 #define CONFIG_HAS_ETH1
778 #ifdef CONFIG_UEC_ETH5
779 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
780 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
781 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
782 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
783 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
784 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
785 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
786 #endif /* CONFIG_UEC_ETH5 */
787 #endif /* CONFIG_TARGET_P1025RDB */
792 #ifdef CONFIG_SPIFLASH
793 #define CONFIG_ENV_IS_IN_SPI_FLASH
794 #define CONFIG_ENV_SPI_BUS 0
795 #define CONFIG_ENV_SPI_CS 0
796 #define CONFIG_ENV_SPI_MAX_HZ 10000000
797 #define CONFIG_ENV_SPI_MODE 0
798 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
799 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
800 #define CONFIG_ENV_SECT_SIZE 0x10000
801 #elif defined(CONFIG_SDCARD)
802 #define CONFIG_ENV_IS_IN_MMC
803 #define CONFIG_FSL_FIXED_MMC_LOCATION
804 #define CONFIG_ENV_SIZE 0x2000
805 #define CONFIG_SYS_MMC_ENV_DEV 0
806 #elif defined(CONFIG_NAND)
807 #ifdef CONFIG_TPL_BUILD
808 #define CONFIG_ENV_SIZE 0x2000
809 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
811 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
813 #define CONFIG_ENV_IS_IN_NAND
814 #define CONFIG_ENV_OFFSET (1024 * 1024)
815 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
816 #elif defined(CONFIG_SYS_RAMBOOT)
817 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
818 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
819 #define CONFIG_ENV_SIZE 0x2000
821 #define CONFIG_ENV_IS_IN_FLASH
822 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
823 #define CONFIG_ENV_SIZE 0x2000
824 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
827 #define CONFIG_LOADS_ECHO /* echo on for serial download */
828 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
831 * Command line configuration.
833 #define CONFIG_CMD_IRQ
834 #define CONFIG_CMD_DATE
835 #define CONFIG_CMD_REGINFO
840 #define CONFIG_HAS_FSL_DR_USB
842 #if defined(CONFIG_HAS_FSL_DR_USB)
843 #define CONFIG_USB_EHCI
845 #ifdef CONFIG_USB_EHCI
846 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
847 #define CONFIG_USB_EHCI_FSL
851 #if defined(CONFIG_TARGET_P1020RDB_PD)
852 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
858 #define CONFIG_FSL_ESDHC
859 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
860 #define CONFIG_GENERIC_MMC
863 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
864 || defined(CONFIG_FSL_SATA)
865 #define CONFIG_DOS_PARTITION
868 #undef CONFIG_WATCHDOG /* watchdog disabled */
871 * Miscellaneous configurable options
873 #define CONFIG_SYS_LONGHELP /* undef to save memory */
874 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
875 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
876 #if defined(CONFIG_CMD_KGDB)
877 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
879 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
881 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
882 /* Print Buffer Size */
883 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
884 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
887 * For booting Linux, the board info and command line data
888 * have to be in the first 64 MB of memory, since this is
889 * the maximum mapped by the Linux kernel during initialization.
891 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
892 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
894 #if defined(CONFIG_CMD_KGDB)
895 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
899 * Environment Configuration
901 #define CONFIG_HOSTNAME unknown
902 #define CONFIG_ROOTPATH "/opt/nfsroot"
903 #define CONFIG_BOOTFILE "uImage"
904 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
906 /* default location for tftp and bootm */
907 #define CONFIG_LOADADDR 1000000
909 #define CONFIG_BOOTARGS /* the boot command will set bootargs */
911 #define CONFIG_BAUDRATE 115200
914 #define __NOR_RST_CMD \
915 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
916 i2c mw 18 3 __SW_BOOT_MASK 1; reset
919 #define __SPI_RST_CMD \
920 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
921 i2c mw 18 3 __SW_BOOT_MASK 1; reset
924 #define __SD_RST_CMD \
925 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
926 i2c mw 18 3 __SW_BOOT_MASK 1; reset
928 #ifdef __SW_BOOT_NAND
929 #define __NAND_RST_CMD \
930 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
931 i2c mw 18 3 __SW_BOOT_MASK 1; reset
933 #ifdef __SW_BOOT_PCIE
934 #define __PCIE_RST_CMD \
935 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
936 i2c mw 18 3 __SW_BOOT_MASK 1; reset
939 #define CONFIG_EXTRA_ENV_SETTINGS \
941 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
942 "loadaddr=1000000\0" \
943 "bootfile=uImage\0" \
944 "tftpflash=tftpboot $loadaddr $uboot; " \
945 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
946 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
947 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
948 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
949 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
950 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
951 "consoledev=ttyS0\0" \
952 "ramdiskaddr=2000000\0" \
953 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
954 "fdtaddr=1e00000\0" \
956 "jffs2nor=mtdblock3\0" \
957 "norbootaddr=ef080000\0" \
958 "norfdtaddr=ef040000\0" \
959 "jffs2nand=mtdblock9\0" \
960 "nandbootaddr=100000\0" \
961 "nandfdtaddr=80000\0" \
962 "ramdisk_size=120000\0" \
963 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
964 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
965 __stringify(__NOR_RST_CMD)"\0" \
966 __stringify(__SPI_RST_CMD)"\0" \
967 __stringify(__SD_RST_CMD)"\0" \
968 __stringify(__NAND_RST_CMD)"\0" \
969 __stringify(__PCIE_RST_CMD)"\0"
971 #define CONFIG_NFSBOOTCOMMAND \
972 "setenv bootargs root=/dev/nfs rw " \
973 "nfsroot=$serverip:$rootpath " \
974 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
975 "console=$consoledev,$baudrate $othbootargs;" \
976 "tftp $loadaddr $bootfile;" \
977 "tftp $fdtaddr $fdtfile;" \
978 "bootm $loadaddr - $fdtaddr"
980 #define CONFIG_HDBOOT \
981 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
982 "console=$consoledev,$baudrate $othbootargs;" \
984 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
985 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
986 "bootm $loadaddr - $fdtaddr"
988 #define CONFIG_USB_FAT_BOOT \
989 "setenv bootargs root=/dev/ram rw " \
990 "console=$consoledev,$baudrate $othbootargs " \
991 "ramdisk_size=$ramdisk_size;" \
993 "fatload usb 0:2 $loadaddr $bootfile;" \
994 "fatload usb 0:2 $fdtaddr $fdtfile;" \
995 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
996 "bootm $loadaddr $ramdiskaddr $fdtaddr"
998 #define CONFIG_USB_EXT2_BOOT \
999 "setenv bootargs root=/dev/ram rw " \
1000 "console=$consoledev,$baudrate $othbootargs " \
1001 "ramdisk_size=$ramdisk_size;" \
1003 "ext2load usb 0:4 $loadaddr $bootfile;" \
1004 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
1005 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
1006 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1008 #define CONFIG_NORBOOT \
1009 "setenv bootargs root=/dev/$jffs2nor rw " \
1010 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
1011 "bootm $norbootaddr - $norfdtaddr"
1013 #define CONFIG_RAMBOOTCOMMAND \
1014 "setenv bootargs root=/dev/ram rw " \
1015 "console=$consoledev,$baudrate $othbootargs " \
1016 "ramdisk_size=$ramdisk_size;" \
1017 "tftp $ramdiskaddr $ramdiskfile;" \
1018 "tftp $loadaddr $bootfile;" \
1019 "tftp $fdtaddr $fdtfile;" \
1020 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1022 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
1024 #endif /* __CONFIG_H */