1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * QorIQ RDB boards configuration file
13 #include <linux/stringify.h>
15 #if defined(CONFIG_TARGET_P1020RDB_PC)
16 #define CONFIG_BOARDNAME "P1020RDB-PC"
17 #define CONFIG_VSC7385_ENET
19 #define __SW_BOOT_MASK 0x03
20 #define __SW_BOOT_NOR 0x5c
21 #define __SW_BOOT_SPI 0x1c
22 #define __SW_BOOT_SD 0x9c
23 #define __SW_BOOT_NAND 0xec
24 #define __SW_BOOT_PCIE 0x6c
25 #define CONFIG_SYS_L2_SIZE (256 << 10)
29 * P1020RDB-PD board has user selectable switches for evaluating different
30 * frequency and boot options for the P1020 device. The table that
31 * follow describe the available options. The front six binary number was in
32 * accordance with SW3[1:6].
33 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
34 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
35 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
36 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
37 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
38 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
39 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
41 #if defined(CONFIG_TARGET_P1020RDB_PD)
42 #define CONFIG_BOARDNAME "P1020RDB-PD"
43 #define CONFIG_VSC7385_ENET
45 #define __SW_BOOT_MASK 0x03
46 #define __SW_BOOT_NOR 0x64
47 #define __SW_BOOT_SPI 0x34
48 #define __SW_BOOT_SD 0x24
49 #define __SW_BOOT_NAND 0x44
50 #define __SW_BOOT_PCIE 0x74
51 #define CONFIG_SYS_L2_SIZE (256 << 10)
53 * Dynamic MTD Partition support with mtdparts
57 #if defined(CONFIG_TARGET_P2020RDB)
58 #define CONFIG_BOARDNAME "P2020RDB-PC"
59 #define CONFIG_VSC7385_ENET
60 #define __SW_BOOT_MASK 0x03
61 #define __SW_BOOT_NOR 0xc8
62 #define __SW_BOOT_SPI 0x28
63 #define __SW_BOOT_SD 0x68 /* or 0x18 */
64 #define __SW_BOOT_NAND 0xe8
65 #define __SW_BOOT_PCIE 0xa8
66 #define CONFIG_SYS_L2_SIZE (512 << 10)
68 * Dynamic MTD Partition support with mtdparts
73 #define CONFIG_SPL_FLUSH_IMAGE
74 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
75 #define CONFIG_SPL_PAD_TO 0x20000
76 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
77 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
78 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
79 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
80 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
81 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
82 #ifdef CONFIG_SPL_BUILD
83 #define CONFIG_SPL_COMMON_INIT_DDR
85 #elif defined(CONFIG_SPIFLASH)
86 #define CONFIG_SPL_SPI_FLASH_MINIMAL
87 #define CONFIG_SPL_FLUSH_IMAGE
88 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
89 #define CONFIG_SPL_PAD_TO 0x20000
90 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
91 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
92 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
93 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
94 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
95 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
96 #ifdef CONFIG_SPL_BUILD
97 #define CONFIG_SPL_COMMON_INIT_DDR
99 #elif defined(CONFIG_MTD_RAW_NAND)
100 #ifdef CONFIG_TPL_BUILD
101 #define CONFIG_SPL_FLUSH_IMAGE
102 #define CONFIG_SPL_NAND_INIT
103 #define CONFIG_SPL_COMMON_INIT_DDR
104 #define CONFIG_SPL_MAX_SIZE (128 << 10)
105 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
106 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
107 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
108 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
109 #elif defined(CONFIG_SPL_BUILD)
110 #define CONFIG_SPL_INIT_MINIMAL
111 #define CONFIG_SPL_FLUSH_IMAGE
112 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
113 #define CONFIG_SPL_MAX_SIZE 4096
114 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
115 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
116 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
117 #endif /* not CONFIG_TPL_BUILD */
119 #define CONFIG_SPL_PAD_TO 0x20000
120 #define CONFIG_TPL_PAD_TO 0x20000
121 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
124 #ifndef CONFIG_RESET_VECTOR_ADDRESS
125 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
128 #ifndef CONFIG_SYS_MONITOR_BASE
129 #ifdef CONFIG_TPL_BUILD
130 #define CONFIG_SYS_MONITOR_BASE 0xf8f81000
131 #elif defined(CONFIG_SPL_BUILD)
132 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
134 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
138 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
139 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
143 #define CONFIG_HWCONFIG
145 * These can be toggled for performance analysis, otherwise use default.
147 #define CONFIG_L2_CACHE
149 #define CONFIG_ENABLE_36BIT_PHYS
151 #define CONFIG_SYS_CCSRBAR 0xffe00000
152 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
154 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
156 #ifdef CONFIG_SPL_BUILD
157 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
161 #define CONFIG_SYS_DDR_RAW_TIMING
162 #define CONFIG_SYS_SPD_BUS_NUM 1
163 #define SPD_EEPROM_ADDRESS 0x52
165 #if defined(CONFIG_TARGET_P1020RDB_PD)
166 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
167 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
169 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
170 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
172 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
173 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
174 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
176 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
178 /* Default settings for DDR3 */
179 #ifndef CONFIG_TARGET_P2020RDB
180 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
181 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
182 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
183 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
184 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
185 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
187 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
188 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
189 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
190 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
192 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
193 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
194 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
195 #define CONFIG_SYS_DDR_RCW_1 0x00000000
196 #define CONFIG_SYS_DDR_RCW_2 0x00000000
197 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
198 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
199 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
200 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
202 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
203 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
204 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
205 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
206 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
207 #define CONFIG_SYS_DDR_MODE_1 0x40461520
208 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
209 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
215 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
216 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
217 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
218 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
220 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
221 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
222 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
223 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
224 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
225 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
226 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
230 * Local Bus Definitions
232 #if defined(CONFIG_TARGET_P1020RDB_PD)
233 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
234 #define CONFIG_SYS_FLASH_BASE 0xec000000
236 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
237 #define CONFIG_SYS_FLASH_BASE 0xef000000
240 #ifdef CONFIG_PHYS_64BIT
241 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
243 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
246 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
249 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
251 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
252 #define CONFIG_SYS_FLASH_QUIET_TEST
253 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
255 #undef CONFIG_SYS_FLASH_CHECKSUM
256 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
257 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
259 #define CONFIG_SYS_FLASH_EMPTY_INFO
262 #ifdef CONFIG_NAND_FSL_ELBC
263 #define CONFIG_SYS_NAND_BASE 0xff800000
264 #ifdef CONFIG_PHYS_64BIT
265 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
267 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
270 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
271 #define CONFIG_SYS_MAX_NAND_DEVICE 1
273 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
274 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
275 | BR_PS_8 /* Port Size = 8 bit */ \
276 | BR_MS_FCM /* MSEL = FCM */ \
278 #if defined(CONFIG_TARGET_P1020RDB_PD)
279 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
280 | OR_FCM_PGS /* Large Page*/ \
288 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
296 #endif /* CONFIG_NAND_FSL_ELBC */
298 #define CONFIG_SYS_INIT_RAM_LOCK
299 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
300 #ifdef CONFIG_PHYS_64BIT
301 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
302 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
303 /* The assembler doesn't like typecast */
304 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
305 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
306 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
308 /* Initial L1 address */
309 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
310 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
311 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
313 /* Size of used area in RAM */
314 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
316 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
317 GENERATED_GBL_DATA_SIZE)
318 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
320 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
322 #define CONFIG_SYS_CPLD_BASE 0xffa00000
323 #ifdef CONFIG_PHYS_64BIT
324 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
326 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
328 /* CPLD config size: 1Mb */
329 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
331 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
333 #define CONFIG_SYS_PMC_BASE 0xff980000
334 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
335 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
337 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
338 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
342 #ifdef CONFIG_VSC7385_ENET
343 #define __VSCFW_ADDR "vscfw_addr=ef000000"
344 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
346 #ifdef CONFIG_PHYS_64BIT
347 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
349 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
352 #define CONFIG_SYS_VSC7385_BR_PRELIM \
353 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
354 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
355 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
356 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
358 /* The size of the VSC7385 firmware image */
359 #define CONFIG_VSC7385_IMAGE_SIZE 8192
363 * Config the L2 Cache as L2 SRAM
365 #if defined(CONFIG_SPL_BUILD)
366 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
367 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
368 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
369 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
370 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
371 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
372 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
373 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
374 #if defined(CONFIG_TARGET_P2020RDB)
375 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
377 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
379 #elif defined(CONFIG_MTD_RAW_NAND)
380 #ifdef CONFIG_TPL_BUILD
381 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
382 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
383 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
384 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
385 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
386 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
387 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
388 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
390 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
391 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
392 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
393 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
394 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
395 #endif /* CONFIG_TPL_BUILD */
399 /* Serial Port - controlled on board with jumper J8
403 #undef CONFIG_SERIAL_SOFTWARE_FIFO
404 #define CONFIG_SYS_NS16550_SERIAL
405 #define CONFIG_SYS_NS16550_REG_SIZE 1
406 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
407 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
408 #define CONFIG_NS16550_MIN_FUNCTIONS
411 #define CONFIG_SYS_BAUDRATE_TABLE \
412 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
414 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
415 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
418 #if !CONFIG_IS_ENABLED(DM_I2C)
419 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
422 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
428 #define CONFIG_RTC_PT7C4338
429 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
430 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
432 /* enable read and write access to EEPROM */
434 #if defined(CONFIG_PCI)
437 * Memory space is mapped 1-1, but I/O space must start from 0.
440 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
441 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
442 #ifdef CONFIG_PHYS_64BIT
443 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
445 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
447 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
448 #ifdef CONFIG_PHYS_64BIT
449 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
451 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
454 /* controller 1, Slot 2, tgtid 1, Base address a000 */
455 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
456 #ifdef CONFIG_PHYS_64BIT
457 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
459 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
461 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
462 #ifdef CONFIG_PHYS_64BIT
463 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
465 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
468 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
469 #endif /* CONFIG_PCI */
471 #if defined(CONFIG_TSEC_ENET)
473 #define CONFIG_TSEC1_NAME "eTSEC1"
475 #define CONFIG_TSEC2_NAME "eTSEC2"
477 #define CONFIG_TSEC3_NAME "eTSEC3"
479 #define TSEC1_PHY_ADDR 2
480 #define TSEC2_PHY_ADDR 0
481 #define TSEC3_PHY_ADDR 1
483 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
484 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
485 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
487 #define TSEC1_PHYIDX 0
488 #define TSEC2_PHYIDX 0
489 #define TSEC3_PHYIDX 0
491 #define CONFIG_ETHPRIME "eTSEC1"
493 #define CONFIG_HAS_ETH0
494 #define CONFIG_HAS_ETH1
495 #define CONFIG_HAS_ETH2
496 #endif /* CONFIG_TSEC_ENET */
501 #if defined(CONFIG_SDCARD)
502 #define CONFIG_FSL_FIXED_MMC_LOCATION
503 #elif defined(CONFIG_MTD_RAW_NAND)
504 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
505 #ifdef CONFIG_TPL_BUILD
506 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
508 #elif defined(CONFIG_SYS_RAMBOOT)
509 #define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
512 #define CONFIG_LOADS_ECHO /* echo on for serial download */
513 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
518 #define CONFIG_HAS_FSL_DR_USB
520 #if defined(CONFIG_HAS_FSL_DR_USB)
521 #ifdef CONFIG_USB_EHCI_HCD
522 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
526 #if defined(CONFIG_TARGET_P1020RDB_PD)
527 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
531 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
535 * Miscellaneous configurable options
539 * For booting Linux, the board info and command line data
540 * have to be in the first 64 MB of memory, since this is
541 * the maximum mapped by the Linux kernel during initialization.
543 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
544 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
547 * Environment Configuration
549 #define CONFIG_HOSTNAME "unknown"
550 #define CONFIG_ROOTPATH "/opt/nfsroot"
551 #define CONFIG_BOOTFILE "uImage"
552 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
555 #define __NOR_RST_CMD \
556 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
557 i2c mw 18 3 __SW_BOOT_MASK 1; reset
560 #define __SPI_RST_CMD \
561 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
562 i2c mw 18 3 __SW_BOOT_MASK 1; reset
565 #define __SD_RST_CMD \
566 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
567 i2c mw 18 3 __SW_BOOT_MASK 1; reset
569 #ifdef __SW_BOOT_NAND
570 #define __NAND_RST_CMD \
571 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
572 i2c mw 18 3 __SW_BOOT_MASK 1; reset
574 #ifdef __SW_BOOT_PCIE
575 #define __PCIE_RST_CMD \
576 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
577 i2c mw 18 3 __SW_BOOT_MASK 1; reset
580 #define CONFIG_EXTRA_ENV_SETTINGS \
582 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
583 "loadaddr=1000000\0" \
584 "bootfile=uImage\0" \
585 "tftpflash=tftpboot $loadaddr $uboot; " \
586 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
587 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
588 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
589 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
590 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
591 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
592 "consoledev=ttyS0\0" \
593 "ramdiskaddr=2000000\0" \
594 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
595 "fdtaddr=1e00000\0" \
597 "jffs2nor=mtdblock3\0" \
598 "norbootaddr=ef080000\0" \
599 "norfdtaddr=ef040000\0" \
600 "jffs2nand=mtdblock9\0" \
601 "nandbootaddr=100000\0" \
602 "nandfdtaddr=80000\0" \
603 "ramdisk_size=120000\0" \
604 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
605 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
606 __stringify(__VSCFW_ADDR)"\0" \
607 __stringify(__NOR_RST_CMD)"\0" \
608 __stringify(__SPI_RST_CMD)"\0" \
609 __stringify(__SD_RST_CMD)"\0" \
610 __stringify(__NAND_RST_CMD)"\0" \
611 __stringify(__PCIE_RST_CMD)"\0"
613 #define CONFIG_USB_FAT_BOOT \
614 "setenv bootargs root=/dev/ram rw " \
615 "console=$consoledev,$baudrate $othbootargs " \
616 "ramdisk_size=$ramdisk_size;" \
618 "fatload usb 0:2 $loadaddr $bootfile;" \
619 "fatload usb 0:2 $fdtaddr $fdtfile;" \
620 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
621 "bootm $loadaddr $ramdiskaddr $fdtaddr"
623 #define CONFIG_USB_EXT2_BOOT \
624 "setenv bootargs root=/dev/ram rw " \
625 "console=$consoledev,$baudrate $othbootargs " \
626 "ramdisk_size=$ramdisk_size;" \
628 "ext2load usb 0:4 $loadaddr $bootfile;" \
629 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
630 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
631 "bootm $loadaddr $ramdiskaddr $fdtaddr"
633 #define CONFIG_NORBOOT \
634 "setenv bootargs root=/dev/$jffs2nor rw " \
635 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
636 "bootm $norbootaddr - $norfdtaddr"
638 #endif /* __CONFIG_H */