1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * QorIQ RDB boards configuration file
13 #include <linux/stringify.h>
15 #if defined(CONFIG_TARGET_P1020RDB_PC)
16 #define CONFIG_VSC7385_ENET
18 #define __SW_BOOT_MASK 0x03
19 #define __SW_BOOT_NOR 0x5c
20 #define __SW_BOOT_SPI 0x1c
21 #define __SW_BOOT_SD 0x9c
22 #define __SW_BOOT_NAND 0xec
23 #define __SW_BOOT_PCIE 0x6c
24 #define CONFIG_SYS_L2_SIZE (256 << 10)
28 * P1020RDB-PD board has user selectable switches for evaluating different
29 * frequency and boot options for the P1020 device. The table that
30 * follow describe the available options. The front six binary number was in
31 * accordance with SW3[1:6].
32 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
33 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
34 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
35 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
36 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
37 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
38 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
40 #if defined(CONFIG_TARGET_P1020RDB_PD)
41 #define CONFIG_VSC7385_ENET
43 #define __SW_BOOT_MASK 0x03
44 #define __SW_BOOT_NOR 0x64
45 #define __SW_BOOT_SPI 0x34
46 #define __SW_BOOT_SD 0x24
47 #define __SW_BOOT_NAND 0x44
48 #define __SW_BOOT_PCIE 0x74
49 #define CONFIG_SYS_L2_SIZE (256 << 10)
51 * Dynamic MTD Partition support with mtdparts
55 #if defined(CONFIG_TARGET_P2020RDB)
56 #define CONFIG_VSC7385_ENET
57 #define __SW_BOOT_MASK 0x03
58 #define __SW_BOOT_NOR 0xc8
59 #define __SW_BOOT_SPI 0x28
60 #define __SW_BOOT_SD 0x68 /* or 0x18 */
61 #define __SW_BOOT_NAND 0xe8
62 #define __SW_BOOT_PCIE 0xa8
63 #define CONFIG_SYS_L2_SIZE (512 << 10)
65 * Dynamic MTD Partition support with mtdparts
70 #define CONFIG_SPL_FLUSH_IMAGE
71 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
72 #define CONFIG_SPL_PAD_TO 0x20000
73 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
74 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
75 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
76 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
77 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
78 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
79 #ifdef CONFIG_SPL_BUILD
80 #define CONFIG_SPL_COMMON_INIT_DDR
82 #elif defined(CONFIG_SPIFLASH)
83 #define CONFIG_SPL_SPI_FLASH_MINIMAL
84 #define CONFIG_SPL_FLUSH_IMAGE
85 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
86 #define CONFIG_SPL_PAD_TO 0x20000
87 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
88 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
89 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
90 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
91 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
92 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
93 #ifdef CONFIG_SPL_BUILD
94 #define CONFIG_SPL_COMMON_INIT_DDR
96 #elif defined(CONFIG_MTD_RAW_NAND)
97 #ifdef CONFIG_TPL_BUILD
98 #define CONFIG_SPL_FLUSH_IMAGE
99 #define CONFIG_SPL_NAND_INIT
100 #define CONFIG_SPL_COMMON_INIT_DDR
101 #define CONFIG_SPL_MAX_SIZE (128 << 10)
102 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
103 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
104 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
105 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
106 #elif defined(CONFIG_SPL_BUILD)
107 #define CONFIG_SPL_INIT_MINIMAL
108 #define CONFIG_SPL_FLUSH_IMAGE
109 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
110 #define CONFIG_SPL_MAX_SIZE 4096
111 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
112 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
113 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
114 #endif /* not CONFIG_TPL_BUILD */
116 #define CONFIG_SPL_PAD_TO 0x20000
117 #define CONFIG_TPL_PAD_TO 0x20000
118 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
121 #ifndef CONFIG_RESET_VECTOR_ADDRESS
122 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
125 #ifndef CONFIG_SYS_MONITOR_BASE
126 #ifdef CONFIG_TPL_BUILD
127 #define CONFIG_SYS_MONITOR_BASE 0xf8f81000
128 #elif defined(CONFIG_SPL_BUILD)
129 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
131 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
135 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
136 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
140 #define CONFIG_HWCONFIG
142 * These can be toggled for performance analysis, otherwise use default.
144 #define CONFIG_L2_CACHE
146 #define CONFIG_ENABLE_36BIT_PHYS
148 #define CONFIG_SYS_CCSRBAR 0xffe00000
149 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
151 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
153 #ifdef CONFIG_SPL_BUILD
154 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
158 #define CONFIG_SYS_DDR_RAW_TIMING
159 #define CONFIG_SYS_SPD_BUS_NUM 1
160 #define SPD_EEPROM_ADDRESS 0x52
162 #if defined(CONFIG_TARGET_P1020RDB_PD)
163 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
165 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
167 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
168 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
169 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
171 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
173 /* Default settings for DDR3 */
174 #ifndef CONFIG_TARGET_P2020RDB
175 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
176 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
177 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
178 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
179 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
180 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
182 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
183 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
184 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
185 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
187 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
188 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
189 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
190 #define CONFIG_SYS_DDR_RCW_1 0x00000000
191 #define CONFIG_SYS_DDR_RCW_2 0x00000000
192 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
193 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
194 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
195 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
197 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
198 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
199 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
200 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
201 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
202 #define CONFIG_SYS_DDR_MODE_1 0x40461520
203 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
204 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
210 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
211 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
212 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
213 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
215 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
216 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
217 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
218 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
219 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
220 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
221 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
225 * Local Bus Definitions
227 #if defined(CONFIG_TARGET_P1020RDB_PD)
228 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
229 #define CONFIG_SYS_FLASH_BASE 0xec000000
231 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
232 #define CONFIG_SYS_FLASH_BASE 0xef000000
235 #ifdef CONFIG_PHYS_64BIT
236 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
238 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
241 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
244 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
246 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
247 #define CONFIG_SYS_FLASH_QUIET_TEST
248 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
250 #undef CONFIG_SYS_FLASH_CHECKSUM
251 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
252 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
254 #define CONFIG_SYS_FLASH_EMPTY_INFO
257 #ifdef CONFIG_NAND_FSL_ELBC
258 #define CONFIG_SYS_NAND_BASE 0xff800000
259 #ifdef CONFIG_PHYS_64BIT
260 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
262 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
265 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
266 #define CONFIG_SYS_MAX_NAND_DEVICE 1
268 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
269 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
270 | BR_PS_8 /* Port Size = 8 bit */ \
271 | BR_MS_FCM /* MSEL = FCM */ \
273 #if defined(CONFIG_TARGET_P1020RDB_PD)
274 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
275 | OR_FCM_PGS /* Large Page*/ \
283 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
291 #endif /* CONFIG_NAND_FSL_ELBC */
293 #define CONFIG_SYS_INIT_RAM_LOCK
294 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
295 #ifdef CONFIG_PHYS_64BIT
296 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
297 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
298 /* The assembler doesn't like typecast */
299 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
300 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
301 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
303 /* Initial L1 address */
304 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
305 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
306 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
308 /* Size of used area in RAM */
309 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
311 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
312 GENERATED_GBL_DATA_SIZE)
313 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
315 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
317 #define CONFIG_SYS_CPLD_BASE 0xffa00000
318 #ifdef CONFIG_PHYS_64BIT
319 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
321 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
323 /* CPLD config size: 1Mb */
325 #define CONFIG_SYS_PMC_BASE 0xff980000
326 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
327 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
329 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
330 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
334 #ifdef CONFIG_VSC7385_ENET
335 #define __VSCFW_ADDR "vscfw_addr=ef000000"
336 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
338 #ifdef CONFIG_PHYS_64BIT
339 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
341 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
344 #define CONFIG_SYS_VSC7385_BR_PRELIM \
345 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
346 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
347 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
348 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
350 /* The size of the VSC7385 firmware image */
351 #define CONFIG_VSC7385_IMAGE_SIZE 8192
355 * Config the L2 Cache as L2 SRAM
357 #if defined(CONFIG_SPL_BUILD)
358 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
359 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
360 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
361 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
362 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
363 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
364 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
365 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
366 #if defined(CONFIG_TARGET_P2020RDB)
367 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
369 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
371 #elif defined(CONFIG_MTD_RAW_NAND)
372 #ifdef CONFIG_TPL_BUILD
373 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
374 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
375 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
376 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
377 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
378 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
379 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
380 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
382 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
383 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
384 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
385 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
386 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
387 #endif /* CONFIG_TPL_BUILD */
391 /* Serial Port - controlled on board with jumper J8
395 #undef CONFIG_SERIAL_SOFTWARE_FIFO
396 #define CONFIG_SYS_NS16550_SERIAL
397 #define CONFIG_SYS_NS16550_REG_SIZE 1
398 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
399 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
400 #define CONFIG_NS16550_MIN_FUNCTIONS
403 #define CONFIG_SYS_BAUDRATE_TABLE \
404 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
406 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
407 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
410 #if !CONFIG_IS_ENABLED(DM_I2C)
411 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
414 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
420 #define CONFIG_RTC_PT7C4338
421 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
422 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
424 /* enable read and write access to EEPROM */
426 #if defined(CONFIG_PCI)
429 * Memory space is mapped 1-1, but I/O space must start from 0.
432 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
433 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
434 #ifdef CONFIG_PHYS_64BIT
435 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
437 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
439 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
440 #ifdef CONFIG_PHYS_64BIT
441 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
443 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
446 /* controller 1, Slot 2, tgtid 1, Base address a000 */
447 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
448 #ifdef CONFIG_PHYS_64BIT
449 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
451 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
453 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
454 #ifdef CONFIG_PHYS_64BIT
455 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
457 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
460 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
461 #endif /* CONFIG_PCI */
463 #if defined(CONFIG_TSEC_ENET)
465 #define CONFIG_TSEC1_NAME "eTSEC1"
467 #define CONFIG_TSEC2_NAME "eTSEC2"
469 #define CONFIG_TSEC3_NAME "eTSEC3"
471 #define TSEC1_PHY_ADDR 2
472 #define TSEC2_PHY_ADDR 0
473 #define TSEC3_PHY_ADDR 1
475 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
476 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
477 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
479 #define TSEC1_PHYIDX 0
480 #define TSEC2_PHYIDX 0
481 #define TSEC3_PHYIDX 0
482 #endif /* CONFIG_TSEC_ENET */
487 #if defined(CONFIG_SDCARD)
488 #define CONFIG_FSL_FIXED_MMC_LOCATION
489 #elif defined(CONFIG_MTD_RAW_NAND)
490 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
491 #ifdef CONFIG_TPL_BUILD
492 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
494 #elif defined(CONFIG_SYS_RAMBOOT)
495 #define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
498 #define CONFIG_LOADS_ECHO /* echo on for serial download */
499 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
504 #define CONFIG_HAS_FSL_DR_USB
506 #if defined(CONFIG_HAS_FSL_DR_USB)
507 #ifdef CONFIG_USB_EHCI_HCD
508 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
512 #if defined(CONFIG_TARGET_P1020RDB_PD)
513 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
517 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
521 * Miscellaneous configurable options
525 * For booting Linux, the board info and command line data
526 * have to be in the first 64 MB of memory, since this is
527 * the maximum mapped by the Linux kernel during initialization.
529 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
530 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
533 * Environment Configuration
535 #define CONFIG_HOSTNAME "unknown"
536 #define CONFIG_ROOTPATH "/opt/nfsroot"
537 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
540 #define __NOR_RST_CMD \
541 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
542 i2c mw 18 3 __SW_BOOT_MASK 1; reset
545 #define __SPI_RST_CMD \
546 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
547 i2c mw 18 3 __SW_BOOT_MASK 1; reset
550 #define __SD_RST_CMD \
551 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
552 i2c mw 18 3 __SW_BOOT_MASK 1; reset
554 #ifdef __SW_BOOT_NAND
555 #define __NAND_RST_CMD \
556 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
557 i2c mw 18 3 __SW_BOOT_MASK 1; reset
559 #ifdef __SW_BOOT_PCIE
560 #define __PCIE_RST_CMD \
561 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
562 i2c mw 18 3 __SW_BOOT_MASK 1; reset
565 #define CONFIG_EXTRA_ENV_SETTINGS \
567 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
568 "loadaddr=1000000\0" \
569 "bootfile=uImage\0" \
570 "tftpflash=tftpboot $loadaddr $uboot; " \
571 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
572 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
573 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
574 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
575 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
576 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
577 "consoledev=ttyS0\0" \
578 "ramdiskaddr=2000000\0" \
579 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
580 "fdtaddr=1e00000\0" \
582 "jffs2nor=mtdblock3\0" \
583 "norbootaddr=ef080000\0" \
584 "norfdtaddr=ef040000\0" \
585 "jffs2nand=mtdblock9\0" \
586 "nandbootaddr=100000\0" \
587 "nandfdtaddr=80000\0" \
588 "ramdisk_size=120000\0" \
589 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
590 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
591 __stringify(__VSCFW_ADDR)"\0" \
592 __stringify(__NOR_RST_CMD)"\0" \
593 __stringify(__SPI_RST_CMD)"\0" \
594 __stringify(__SD_RST_CMD)"\0" \
595 __stringify(__NAND_RST_CMD)"\0" \
596 __stringify(__PCIE_RST_CMD)"\0"
598 #define CONFIG_USB_FAT_BOOT \
599 "setenv bootargs root=/dev/ram rw " \
600 "console=$consoledev,$baudrate $othbootargs " \
601 "ramdisk_size=$ramdisk_size;" \
603 "fatload usb 0:2 $loadaddr $bootfile;" \
604 "fatload usb 0:2 $fdtaddr $fdtfile;" \
605 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
606 "bootm $loadaddr $ramdiskaddr $fdtaddr"
608 #define CONFIG_USB_EXT2_BOOT \
609 "setenv bootargs root=/dev/ram rw " \
610 "console=$consoledev,$baudrate $othbootargs " \
611 "ramdisk_size=$ramdisk_size;" \
613 "ext2load usb 0:4 $loadaddr $bootfile;" \
614 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
615 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
616 "bootm $loadaddr $ramdiskaddr $fdtaddr"
618 #define CONFIG_NORBOOT \
619 "setenv bootargs root=/dev/$jffs2nor rw " \
620 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
621 "bootm $norbootaddr - $norfdtaddr"
623 #endif /* __CONFIG_H */