2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * QorIQ RDB boards configuration file
13 #if defined(CONFIG_TARGET_P1020MBG)
14 #define CONFIG_BOARDNAME "P1020MBG-PC"
15 #define CONFIG_VSC7385_ENET
17 #define __SW_BOOT_MASK 0x03
18 #define __SW_BOOT_NOR 0xe4
19 #define __SW_BOOT_SD 0x54
20 #define CONFIG_SYS_L2_SIZE (256 << 10)
23 #if defined(CONFIG_TARGET_P1020UTM)
24 #define CONFIG_BOARDNAME "P1020UTM-PC"
25 #define __SW_BOOT_MASK 0x03
26 #define __SW_BOOT_NOR 0xe0
27 #define __SW_BOOT_SD 0x50
28 #define CONFIG_SYS_L2_SIZE (256 << 10)
31 #if defined(CONFIG_TARGET_P1020RDB_PC)
32 #define CONFIG_BOARDNAME "P1020RDB-PC"
33 #define CONFIG_NAND_FSL_ELBC
34 #define CONFIG_VSC7385_ENET
36 #define __SW_BOOT_MASK 0x03
37 #define __SW_BOOT_NOR 0x5c
38 #define __SW_BOOT_SPI 0x1c
39 #define __SW_BOOT_SD 0x9c
40 #define __SW_BOOT_NAND 0xec
41 #define __SW_BOOT_PCIE 0x6c
42 #define CONFIG_SYS_L2_SIZE (256 << 10)
46 * P1020RDB-PD board has user selectable switches for evaluating different
47 * frequency and boot options for the P1020 device. The table that
48 * follow describe the available options. The front six binary number was in
49 * accordance with SW3[1:6].
50 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
51 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
52 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
53 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
54 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
55 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
56 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
58 #if defined(CONFIG_TARGET_P1020RDB_PD)
59 #define CONFIG_BOARDNAME "P1020RDB-PD"
60 #define CONFIG_NAND_FSL_ELBC
61 #define CONFIG_VSC7385_ENET
63 #define __SW_BOOT_MASK 0x03
64 #define __SW_BOOT_NOR 0x64
65 #define __SW_BOOT_SPI 0x34
66 #define __SW_BOOT_SD 0x24
67 #define __SW_BOOT_NAND 0x44
68 #define __SW_BOOT_PCIE 0x74
69 #define CONFIG_SYS_L2_SIZE (256 << 10)
71 * Dynamic MTD Partition support with mtdparts
73 #define CONFIG_MTD_DEVICE
74 #define CONFIG_MTD_PARTITIONS
75 #define CONFIG_CMD_MTDPARTS
76 #define CONFIG_FLASH_CFI_MTD
77 #define MTDIDS_DEFAULT "nor0=ec000000.nor"
78 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \
79 "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
82 #if defined(CONFIG_TARGET_P1021RDB)
83 #define CONFIG_BOARDNAME "P1021RDB-PC"
84 #define CONFIG_NAND_FSL_ELBC
86 #define CONFIG_VSC7385_ENET
87 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
88 addresses in the LBC */
89 #define __SW_BOOT_MASK 0x03
90 #define __SW_BOOT_NOR 0x5c
91 #define __SW_BOOT_SPI 0x1c
92 #define __SW_BOOT_SD 0x9c
93 #define __SW_BOOT_NAND 0xec
94 #define __SW_BOOT_PCIE 0x6c
95 #define CONFIG_SYS_L2_SIZE (256 << 10)
97 * Dynamic MTD Partition support with mtdparts
99 #define CONFIG_MTD_DEVICE
100 #define CONFIG_MTD_PARTITIONS
101 #define CONFIG_CMD_MTDPARTS
102 #define CONFIG_FLASH_CFI_MTD
103 #ifdef CONFIG_PHYS_64BIT
104 #define MTDIDS_DEFAULT "nor0=fef000000.nor"
105 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
106 "256k(dtb),4608k(kernel),9728k(fs)," \
107 "256k(qe-ucode-firmware),1280k(u-boot)"
109 #define MTDIDS_DEFAULT "nor0=ef000000.nor"
110 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
111 "256k(dtb),4608k(kernel),9728k(fs)," \
112 "256k(qe-ucode-firmware),1280k(u-boot)"
116 #if defined(CONFIG_TARGET_P1024RDB)
117 #define CONFIG_BOARDNAME "P1024RDB"
118 #define CONFIG_NAND_FSL_ELBC
120 #define __SW_BOOT_MASK 0xf3
121 #define __SW_BOOT_NOR 0x00
122 #define __SW_BOOT_SPI 0x08
123 #define __SW_BOOT_SD 0x04
124 #define __SW_BOOT_NAND 0x0c
125 #define CONFIG_SYS_L2_SIZE (256 << 10)
128 #if defined(CONFIG_TARGET_P1025RDB)
129 #define CONFIG_BOARDNAME "P1025RDB"
130 #define CONFIG_NAND_FSL_ELBC
135 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
136 addresses in the LBC */
137 #define __SW_BOOT_MASK 0xf3
138 #define __SW_BOOT_NOR 0x00
139 #define __SW_BOOT_SPI 0x08
140 #define __SW_BOOT_SD 0x04
141 #define __SW_BOOT_NAND 0x0c
142 #define CONFIG_SYS_L2_SIZE (256 << 10)
145 #if defined(CONFIG_TARGET_P2020RDB)
146 #define CONFIG_BOARDNAME "P2020RDB-PC"
147 #define CONFIG_NAND_FSL_ELBC
149 #define CONFIG_VSC7385_ENET
150 #define __SW_BOOT_MASK 0x03
151 #define __SW_BOOT_NOR 0xc8
152 #define __SW_BOOT_SPI 0x28
153 #define __SW_BOOT_SD 0x68 /* or 0x18 */
154 #define __SW_BOOT_NAND 0xe8
155 #define __SW_BOOT_PCIE 0xa8
156 #define CONFIG_SYS_L2_SIZE (512 << 10)
158 * Dynamic MTD Partition support with mtdparts
160 #define CONFIG_MTD_DEVICE
161 #define CONFIG_MTD_PARTITIONS
162 #define CONFIG_CMD_MTDPARTS
163 #define CONFIG_FLASH_CFI_MTD
164 #ifdef CONFIG_PHYS_64BIT
165 #define MTDIDS_DEFAULT "nor0=fef000000.nor"
166 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
167 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
169 #define MTDIDS_DEFAULT "nor0=ef000000.nor"
170 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
171 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
176 #define CONFIG_SPL_MMC_MINIMAL
177 #define CONFIG_SPL_FLUSH_IMAGE
178 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
179 #define CONFIG_FSL_LAW /* Use common FSL init code */
180 #define CONFIG_SYS_TEXT_BASE 0x11001000
181 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
182 #define CONFIG_SPL_PAD_TO 0x20000
183 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
184 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
185 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
186 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
187 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
188 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
189 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
190 #define CONFIG_SPL_MMC_BOOT
191 #ifdef CONFIG_SPL_BUILD
192 #define CONFIG_SPL_COMMON_INIT_DDR
196 #ifdef CONFIG_SPIFLASH
197 #define CONFIG_SPL_SPI_FLASH_MINIMAL
198 #define CONFIG_SPL_FLUSH_IMAGE
199 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
200 #define CONFIG_FSL_LAW /* Use common FSL init code */
201 #define CONFIG_SYS_TEXT_BASE 0x11001000
202 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
203 #define CONFIG_SPL_PAD_TO 0x20000
204 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
205 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
206 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
207 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
208 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
209 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
210 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
211 #define CONFIG_SPL_SPI_BOOT
212 #ifdef CONFIG_SPL_BUILD
213 #define CONFIG_SPL_COMMON_INIT_DDR
218 #ifdef CONFIG_TPL_BUILD
219 #define CONFIG_SPL_NAND_BOOT
220 #define CONFIG_SPL_FLUSH_IMAGE
221 #define CONFIG_SPL_NAND_INIT
222 #define CONFIG_SPL_COMMON_INIT_DDR
223 #define CONFIG_SPL_MAX_SIZE (128 << 10)
224 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
225 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
226 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
227 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
228 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
229 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
230 #elif defined(CONFIG_SPL_BUILD)
231 #define CONFIG_SPL_INIT_MINIMAL
232 #define CONFIG_SPL_FLUSH_IMAGE
233 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
234 #define CONFIG_SPL_TEXT_BASE 0xff800000
235 #define CONFIG_SPL_MAX_SIZE 4096
236 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
237 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
238 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
239 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
240 #endif /* not CONFIG_TPL_BUILD */
242 #define CONFIG_SPL_PAD_TO 0x20000
243 #define CONFIG_TPL_PAD_TO 0x20000
244 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
245 #define CONFIG_SYS_TEXT_BASE 0x11001000
246 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
249 #ifndef CONFIG_SYS_TEXT_BASE
250 #define CONFIG_SYS_TEXT_BASE 0xeff40000
253 #ifndef CONFIG_RESET_VECTOR_ADDRESS
254 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
257 #ifndef CONFIG_SYS_MONITOR_BASE
258 #ifdef CONFIG_SPL_BUILD
259 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
261 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
265 /* High Level Configuration Options */
271 #define CONFIG_FSL_ELBC
272 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
273 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
274 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
275 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
276 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
277 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
279 #define CONFIG_FSL_LAW
280 #define CONFIG_TSEC_ENET /* tsec ethernet support */
281 #define CONFIG_ENV_OVERWRITE
283 #define CONFIG_CMD_SATA
284 #define CONFIG_SATA_SIL
285 #define CONFIG_SYS_SATA_MAX_DEVICE 2
286 #define CONFIG_LIBATA
289 #if defined(CONFIG_TARGET_P2020RDB)
290 #define CONFIG_SYS_CLK_FREQ 100000000
292 #define CONFIG_SYS_CLK_FREQ 66666666
294 #define CONFIG_DDR_CLK_FREQ 66666666
296 #define CONFIG_HWCONFIG
298 * These can be toggled for performance analysis, otherwise use default.
300 #define CONFIG_L2_CACHE
303 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
305 #define CONFIG_ENABLE_36BIT_PHYS
307 #ifdef CONFIG_PHYS_64BIT
308 #define CONFIG_ADDR_MAP 1
309 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
312 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
313 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
314 #define CONFIG_PANIC_HANG /* do not reset board on panic */
316 #define CONFIG_SYS_CCSRBAR 0xffe00000
317 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
319 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
321 #ifdef CONFIG_SPL_BUILD
322 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
326 #define CONFIG_SYS_FSL_DDR3
327 #define CONFIG_SYS_DDR_RAW_TIMING
328 #define CONFIG_DDR_SPD
329 #define CONFIG_SYS_SPD_BUS_NUM 1
330 #define SPD_EEPROM_ADDRESS 0x52
331 #undef CONFIG_FSL_DDR_INTERACTIVE
333 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
334 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
335 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
337 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
338 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
340 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
341 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
342 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
344 #define CONFIG_NUM_DDR_CONTROLLERS 1
345 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
347 /* Default settings for DDR3 */
348 #ifndef CONFIG_TARGET_P2020RDB
349 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
350 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
351 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
352 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
353 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
354 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
356 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
357 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
358 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
359 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
361 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
362 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
363 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
364 #define CONFIG_SYS_DDR_RCW_1 0x00000000
365 #define CONFIG_SYS_DDR_RCW_2 0x00000000
366 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
367 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
368 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
369 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
371 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
372 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
373 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
374 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
375 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
376 #define CONFIG_SYS_DDR_MODE_1 0x40461520
377 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
378 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
381 #undef CONFIG_CLOCKS_IN_MHZ
386 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
387 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
388 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
389 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
391 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
392 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
393 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
394 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
395 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
396 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
397 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
401 * Local Bus Definitions
403 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
404 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
405 #define CONFIG_SYS_FLASH_BASE 0xec000000
406 #elif defined(CONFIG_TARGET_P1020UTM)
407 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
408 #define CONFIG_SYS_FLASH_BASE 0xee000000
410 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
411 #define CONFIG_SYS_FLASH_BASE 0xef000000
414 #ifdef CONFIG_PHYS_64BIT
415 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
417 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
420 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
423 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
425 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
426 #define CONFIG_SYS_FLASH_QUIET_TEST
427 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
429 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
431 #undef CONFIG_SYS_FLASH_CHECKSUM
432 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
433 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
435 #define CONFIG_FLASH_CFI_DRIVER
436 #define CONFIG_SYS_FLASH_CFI
437 #define CONFIG_SYS_FLASH_EMPTY_INFO
438 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
441 #ifdef CONFIG_NAND_FSL_ELBC
442 #define CONFIG_SYS_NAND_BASE 0xff800000
443 #ifdef CONFIG_PHYS_64BIT
444 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
446 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
449 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
450 #define CONFIG_SYS_MAX_NAND_DEVICE 1
451 #define CONFIG_CMD_NAND
452 #if defined(CONFIG_TARGET_P1020RDB_PD)
453 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
455 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
458 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
459 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
460 | BR_PS_8 /* Port Size = 8 bit */ \
461 | BR_MS_FCM /* MSEL = FCM */ \
463 #if defined(CONFIG_TARGET_P1020RDB_PD)
464 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
465 | OR_FCM_PGS /* Large Page*/ \
473 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
481 #endif /* CONFIG_NAND_FSL_ELBC */
483 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
485 #define CONFIG_SYS_INIT_RAM_LOCK
486 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
487 #ifdef CONFIG_PHYS_64BIT
488 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
489 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
490 /* The assembler doesn't like typecast */
491 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
492 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
493 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
495 /* Initial L1 address */
496 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
497 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
498 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
500 /* Size of used area in RAM */
501 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
503 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
504 GENERATED_GBL_DATA_SIZE)
505 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
507 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
508 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
510 #define CONFIG_SYS_CPLD_BASE 0xffa00000
511 #ifdef CONFIG_PHYS_64BIT
512 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
514 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
516 /* CPLD config size: 1Mb */
517 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
519 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
521 #define CONFIG_SYS_PMC_BASE 0xff980000
522 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
523 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
525 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
526 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
530 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
531 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
532 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
533 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
535 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
536 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
537 #ifdef CONFIG_NAND_FSL_ELBC
538 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
539 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
542 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
543 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
546 #ifdef CONFIG_VSC7385_ENET
547 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
549 #ifdef CONFIG_PHYS_64BIT
550 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
552 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
555 #define CONFIG_SYS_VSC7385_BR_PRELIM \
556 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
557 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
558 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
559 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
561 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
562 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
564 /* The size of the VSC7385 firmware image */
565 #define CONFIG_VSC7385_IMAGE_SIZE 8192
569 * Config the L2 Cache as L2 SRAM
571 #if defined(CONFIG_SPL_BUILD)
572 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
573 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
574 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
575 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
576 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
577 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
578 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
579 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
580 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
581 #if defined(CONFIG_TARGET_P2020RDB)
582 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
584 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
586 #elif defined(CONFIG_NAND)
587 #ifdef CONFIG_TPL_BUILD
588 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
589 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
590 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
591 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
592 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
593 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
594 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
595 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
597 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
598 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
599 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
600 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
601 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
602 #endif /* CONFIG_TPL_BUILD */
606 /* Serial Port - controlled on board with jumper J8
610 #define CONFIG_CONS_INDEX 1
611 #undef CONFIG_SERIAL_SOFTWARE_FIFO
612 #define CONFIG_SYS_NS16550_SERIAL
613 #define CONFIG_SYS_NS16550_REG_SIZE 1
614 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
615 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
616 #define CONFIG_NS16550_MIN_FUNCTIONS
619 #define CONFIG_SYS_BAUDRATE_TABLE \
620 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
622 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
623 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
626 #define CONFIG_SYS_I2C
627 #define CONFIG_SYS_I2C_FSL
628 #define CONFIG_SYS_FSL_I2C_SPEED 400000
629 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
630 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
631 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
632 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
633 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
634 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
635 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
636 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
641 #undef CONFIG_ID_EEPROM
643 #define CONFIG_RTC_PT7C4338
644 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
645 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
647 /* enable read and write access to EEPROM */
648 #define CONFIG_CMD_EEPROM
649 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
650 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
651 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
654 * eSPI - Enhanced SPI
656 #define CONFIG_HARD_SPI
658 #if defined(CONFIG_SPI_FLASH)
659 #define CONFIG_SF_DEFAULT_SPEED 10000000
660 #define CONFIG_SF_DEFAULT_MODE 0
663 #if defined(CONFIG_PCI)
666 * Memory space is mapped 1-1, but I/O space must start from 0.
669 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
670 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
671 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
672 #ifdef CONFIG_PHYS_64BIT
673 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
674 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
676 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
677 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
679 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
680 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
681 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
682 #ifdef CONFIG_PHYS_64BIT
683 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
685 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
687 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
689 /* controller 1, Slot 2, tgtid 1, Base address a000 */
690 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
691 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
692 #ifdef CONFIG_PHYS_64BIT
693 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
694 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
696 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
697 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
699 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
700 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
701 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
702 #ifdef CONFIG_PHYS_64BIT
703 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
705 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
707 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
709 #define CONFIG_CMD_PCI
711 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
712 #define CONFIG_DOS_PARTITION
713 #endif /* CONFIG_PCI */
715 #if defined(CONFIG_TSEC_ENET)
716 #define CONFIG_MII /* MII PHY management */
718 #define CONFIG_TSEC1_NAME "eTSEC1"
720 #define CONFIG_TSEC2_NAME "eTSEC2"
722 #define CONFIG_TSEC3_NAME "eTSEC3"
724 #define TSEC1_PHY_ADDR 2
725 #define TSEC2_PHY_ADDR 0
726 #define TSEC3_PHY_ADDR 1
728 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
729 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
730 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
732 #define TSEC1_PHYIDX 0
733 #define TSEC2_PHYIDX 0
734 #define TSEC3_PHYIDX 0
736 #define CONFIG_ETHPRIME "eTSEC1"
738 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
740 #define CONFIG_HAS_ETH0
741 #define CONFIG_HAS_ETH1
742 #define CONFIG_HAS_ETH2
743 #endif /* CONFIG_TSEC_ENET */
746 /* QE microcode/firmware address */
747 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
748 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
749 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
750 #endif /* CONFIG_QE */
752 #ifdef CONFIG_TARGET_P1025RDB
754 * QE UEC ethernet configuration
756 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
758 #undef CONFIG_UEC_ETH
759 #define CONFIG_PHY_MODE_NEED_CHANGE
761 #define CONFIG_UEC_ETH1 /* ETH1 */
762 #define CONFIG_HAS_ETH0
764 #ifdef CONFIG_UEC_ETH1
765 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
766 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
767 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
768 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
769 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
770 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
771 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
772 #endif /* CONFIG_UEC_ETH1 */
774 #define CONFIG_UEC_ETH5 /* ETH5 */
775 #define CONFIG_HAS_ETH1
777 #ifdef CONFIG_UEC_ETH5
778 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
779 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
780 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
781 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
782 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
783 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
784 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
785 #endif /* CONFIG_UEC_ETH5 */
786 #endif /* CONFIG_TARGET_P1025RDB */
791 #ifdef CONFIG_SPIFLASH
792 #define CONFIG_ENV_IS_IN_SPI_FLASH
793 #define CONFIG_ENV_SPI_BUS 0
794 #define CONFIG_ENV_SPI_CS 0
795 #define CONFIG_ENV_SPI_MAX_HZ 10000000
796 #define CONFIG_ENV_SPI_MODE 0
797 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
798 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
799 #define CONFIG_ENV_SECT_SIZE 0x10000
800 #elif defined(CONFIG_SDCARD)
801 #define CONFIG_ENV_IS_IN_MMC
802 #define CONFIG_FSL_FIXED_MMC_LOCATION
803 #define CONFIG_ENV_SIZE 0x2000
804 #define CONFIG_SYS_MMC_ENV_DEV 0
805 #elif defined(CONFIG_NAND)
806 #ifdef CONFIG_TPL_BUILD
807 #define CONFIG_ENV_SIZE 0x2000
808 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
810 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
812 #define CONFIG_ENV_IS_IN_NAND
813 #define CONFIG_ENV_OFFSET (1024 * 1024)
814 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
815 #elif defined(CONFIG_SYS_RAMBOOT)
816 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
817 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
818 #define CONFIG_ENV_SIZE 0x2000
820 #define CONFIG_ENV_IS_IN_FLASH
821 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
822 #define CONFIG_ENV_SIZE 0x2000
823 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
826 #define CONFIG_LOADS_ECHO /* echo on for serial download */
827 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
830 * Command line configuration.
832 #define CONFIG_CMD_IRQ
833 #define CONFIG_CMD_DATE
834 #define CONFIG_CMD_REGINFO
839 #define CONFIG_HAS_FSL_DR_USB
841 #if defined(CONFIG_HAS_FSL_DR_USB)
842 #define CONFIG_USB_EHCI
844 #ifdef CONFIG_USB_EHCI
845 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
846 #define CONFIG_USB_EHCI_FSL
850 #if defined(CONFIG_TARGET_P1020RDB_PD)
851 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
857 #define CONFIG_FSL_ESDHC
858 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
859 #define CONFIG_GENERIC_MMC
862 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
863 || defined(CONFIG_FSL_SATA)
864 #define CONFIG_DOS_PARTITION
867 #undef CONFIG_WATCHDOG /* watchdog disabled */
870 * Miscellaneous configurable options
872 #define CONFIG_SYS_LONGHELP /* undef to save memory */
873 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
874 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
875 #if defined(CONFIG_CMD_KGDB)
876 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
878 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
880 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
881 /* Print Buffer Size */
882 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
883 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
886 * For booting Linux, the board info and command line data
887 * have to be in the first 64 MB of memory, since this is
888 * the maximum mapped by the Linux kernel during initialization.
890 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
891 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
893 #if defined(CONFIG_CMD_KGDB)
894 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
898 * Environment Configuration
900 #define CONFIG_HOSTNAME unknown
901 #define CONFIG_ROOTPATH "/opt/nfsroot"
902 #define CONFIG_BOOTFILE "uImage"
903 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
905 /* default location for tftp and bootm */
906 #define CONFIG_LOADADDR 1000000
908 #define CONFIG_BOOTARGS /* the boot command will set bootargs */
910 #define CONFIG_BAUDRATE 115200
913 #define __NOR_RST_CMD \
914 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
915 i2c mw 18 3 __SW_BOOT_MASK 1; reset
918 #define __SPI_RST_CMD \
919 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
920 i2c mw 18 3 __SW_BOOT_MASK 1; reset
923 #define __SD_RST_CMD \
924 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
925 i2c mw 18 3 __SW_BOOT_MASK 1; reset
927 #ifdef __SW_BOOT_NAND
928 #define __NAND_RST_CMD \
929 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
930 i2c mw 18 3 __SW_BOOT_MASK 1; reset
932 #ifdef __SW_BOOT_PCIE
933 #define __PCIE_RST_CMD \
934 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
935 i2c mw 18 3 __SW_BOOT_MASK 1; reset
938 #define CONFIG_EXTRA_ENV_SETTINGS \
940 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
941 "loadaddr=1000000\0" \
942 "bootfile=uImage\0" \
943 "tftpflash=tftpboot $loadaddr $uboot; " \
944 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
945 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
946 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
947 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
948 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
949 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
950 "consoledev=ttyS0\0" \
951 "ramdiskaddr=2000000\0" \
952 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
953 "fdtaddr=1e00000\0" \
955 "jffs2nor=mtdblock3\0" \
956 "norbootaddr=ef080000\0" \
957 "norfdtaddr=ef040000\0" \
958 "jffs2nand=mtdblock9\0" \
959 "nandbootaddr=100000\0" \
960 "nandfdtaddr=80000\0" \
961 "ramdisk_size=120000\0" \
962 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
963 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
964 __stringify(__NOR_RST_CMD)"\0" \
965 __stringify(__SPI_RST_CMD)"\0" \
966 __stringify(__SD_RST_CMD)"\0" \
967 __stringify(__NAND_RST_CMD)"\0" \
968 __stringify(__PCIE_RST_CMD)"\0"
970 #define CONFIG_NFSBOOTCOMMAND \
971 "setenv bootargs root=/dev/nfs rw " \
972 "nfsroot=$serverip:$rootpath " \
973 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
974 "console=$consoledev,$baudrate $othbootargs;" \
975 "tftp $loadaddr $bootfile;" \
976 "tftp $fdtaddr $fdtfile;" \
977 "bootm $loadaddr - $fdtaddr"
979 #define CONFIG_HDBOOT \
980 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
981 "console=$consoledev,$baudrate $othbootargs;" \
983 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
984 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
985 "bootm $loadaddr - $fdtaddr"
987 #define CONFIG_USB_FAT_BOOT \
988 "setenv bootargs root=/dev/ram rw " \
989 "console=$consoledev,$baudrate $othbootargs " \
990 "ramdisk_size=$ramdisk_size;" \
992 "fatload usb 0:2 $loadaddr $bootfile;" \
993 "fatload usb 0:2 $fdtaddr $fdtfile;" \
994 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
995 "bootm $loadaddr $ramdiskaddr $fdtaddr"
997 #define CONFIG_USB_EXT2_BOOT \
998 "setenv bootargs root=/dev/ram rw " \
999 "console=$consoledev,$baudrate $othbootargs " \
1000 "ramdisk_size=$ramdisk_size;" \
1002 "ext2load usb 0:4 $loadaddr $bootfile;" \
1003 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
1004 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
1005 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1007 #define CONFIG_NORBOOT \
1008 "setenv bootargs root=/dev/$jffs2nor rw " \
1009 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
1010 "bootm $norbootaddr - $norfdtaddr"
1012 #define CONFIG_RAMBOOTCOMMAND \
1013 "setenv bootargs root=/dev/ram rw " \
1014 "console=$consoledev,$baudrate $othbootargs " \
1015 "ramdisk_size=$ramdisk_size;" \
1016 "tftp $ramdiskaddr $ramdiskfile;" \
1017 "tftp $loadaddr $bootfile;" \
1018 "tftp $fdtaddr $fdtfile;" \
1019 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1021 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
1023 #endif /* __CONFIG_H */