1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * QorIQ RDB boards configuration file
13 #include <linux/stringify.h>
15 #if defined(CONFIG_TARGET_P1020RDB_PC)
16 #define CONFIG_BOARDNAME "P1020RDB-PC"
17 #define CONFIG_VSC7385_ENET
19 #define __SW_BOOT_MASK 0x03
20 #define __SW_BOOT_NOR 0x5c
21 #define __SW_BOOT_SPI 0x1c
22 #define __SW_BOOT_SD 0x9c
23 #define __SW_BOOT_NAND 0xec
24 #define __SW_BOOT_PCIE 0x6c
25 #define CONFIG_SYS_L2_SIZE (256 << 10)
29 * P1020RDB-PD board has user selectable switches for evaluating different
30 * frequency and boot options for the P1020 device. The table that
31 * follow describe the available options. The front six binary number was in
32 * accordance with SW3[1:6].
33 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
34 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
35 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
36 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
37 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
38 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
39 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
41 #if defined(CONFIG_TARGET_P1020RDB_PD)
42 #define CONFIG_BOARDNAME "P1020RDB-PD"
43 #define CONFIG_VSC7385_ENET
45 #define __SW_BOOT_MASK 0x03
46 #define __SW_BOOT_NOR 0x64
47 #define __SW_BOOT_SPI 0x34
48 #define __SW_BOOT_SD 0x24
49 #define __SW_BOOT_NAND 0x44
50 #define __SW_BOOT_PCIE 0x74
51 #define CONFIG_SYS_L2_SIZE (256 << 10)
53 * Dynamic MTD Partition support with mtdparts
57 #if defined(CONFIG_TARGET_P2020RDB)
58 #define CONFIG_BOARDNAME "P2020RDB-PC"
59 #define CONFIG_VSC7385_ENET
60 #define __SW_BOOT_MASK 0x03
61 #define __SW_BOOT_NOR 0xc8
62 #define __SW_BOOT_SPI 0x28
63 #define __SW_BOOT_SD 0x68 /* or 0x18 */
64 #define __SW_BOOT_NAND 0xe8
65 #define __SW_BOOT_PCIE 0xa8
66 #define CONFIG_SYS_L2_SIZE (512 << 10)
68 * Dynamic MTD Partition support with mtdparts
73 #define CONFIG_SPL_FLUSH_IMAGE
74 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
75 #define CONFIG_SPL_PAD_TO 0x20000
76 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
77 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
78 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
79 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
80 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
81 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
82 #ifdef CONFIG_SPL_BUILD
83 #define CONFIG_SPL_COMMON_INIT_DDR
85 #elif defined(CONFIG_SPIFLASH)
86 #define CONFIG_SPL_SPI_FLASH_MINIMAL
87 #define CONFIG_SPL_FLUSH_IMAGE
88 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
89 #define CONFIG_SPL_PAD_TO 0x20000
90 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
91 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
92 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
93 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
94 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
95 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
96 #ifdef CONFIG_SPL_BUILD
97 #define CONFIG_SPL_COMMON_INIT_DDR
99 #elif defined(CONFIG_MTD_RAW_NAND)
100 #ifdef CONFIG_TPL_BUILD
101 #define CONFIG_SPL_FLUSH_IMAGE
102 #define CONFIG_SPL_NAND_INIT
103 #define CONFIG_SPL_COMMON_INIT_DDR
104 #define CONFIG_SPL_MAX_SIZE (128 << 10)
105 #define CONFIG_TPL_TEXT_BASE 0xf8f81000
106 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
107 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
108 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
109 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
110 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
111 #elif defined(CONFIG_SPL_BUILD)
112 #define CONFIG_SPL_INIT_MINIMAL
113 #define CONFIG_SPL_FLUSH_IMAGE
114 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
115 #define CONFIG_SPL_MAX_SIZE 4096
116 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
117 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
118 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
119 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
120 #endif /* not CONFIG_TPL_BUILD */
122 #define CONFIG_SPL_PAD_TO 0x20000
123 #define CONFIG_TPL_PAD_TO 0x20000
124 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
127 #ifndef CONFIG_RESET_VECTOR_ADDRESS
128 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
131 #ifndef CONFIG_SYS_MONITOR_BASE
132 #ifdef CONFIG_TPL_BUILD
133 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
134 #elif defined(CONFIG_SPL_BUILD)
135 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
137 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
141 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
142 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
143 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
145 #define CONFIG_SYS_SATA_MAX_DEVICE 2
148 #if defined(CONFIG_TARGET_P2020RDB)
149 #define CONFIG_SYS_CLK_FREQ 100000000
151 #define CONFIG_SYS_CLK_FREQ 66666666
154 #define CONFIG_HWCONFIG
156 * These can be toggled for performance analysis, otherwise use default.
158 #define CONFIG_L2_CACHE
161 #define CONFIG_ENABLE_36BIT_PHYS
163 #define CONFIG_SYS_CCSRBAR 0xffe00000
164 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
166 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
168 #ifdef CONFIG_SPL_BUILD
169 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
173 #define CONFIG_SYS_DDR_RAW_TIMING
174 #define CONFIG_SYS_SPD_BUS_NUM 1
175 #define SPD_EEPROM_ADDRESS 0x52
177 #if defined(CONFIG_TARGET_P1020RDB_PD)
178 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
179 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
181 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
182 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
184 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
185 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
186 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
188 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
190 /* Default settings for DDR3 */
191 #ifndef CONFIG_TARGET_P2020RDB
192 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
193 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
194 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
195 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
196 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
197 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
199 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
200 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
201 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
202 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
204 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
205 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
206 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
207 #define CONFIG_SYS_DDR_RCW_1 0x00000000
208 #define CONFIG_SYS_DDR_RCW_2 0x00000000
209 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
210 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
211 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
212 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
214 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
215 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
216 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
217 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
218 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
219 #define CONFIG_SYS_DDR_MODE_1 0x40461520
220 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
221 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
227 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
228 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
229 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
230 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
232 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
233 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
234 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
235 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
236 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
237 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
238 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
242 * Local Bus Definitions
244 #if defined(CONFIG_TARGET_P1020RDB_PD)
245 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
246 #define CONFIG_SYS_FLASH_BASE 0xec000000
248 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
249 #define CONFIG_SYS_FLASH_BASE 0xef000000
252 #ifdef CONFIG_PHYS_64BIT
253 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
255 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
258 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
261 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
263 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
264 #define CONFIG_SYS_FLASH_QUIET_TEST
265 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
267 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
269 #undef CONFIG_SYS_FLASH_CHECKSUM
270 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
271 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
273 #define CONFIG_SYS_FLASH_EMPTY_INFO
276 #ifdef CONFIG_NAND_FSL_ELBC
277 #define CONFIG_SYS_NAND_BASE 0xff800000
278 #ifdef CONFIG_PHYS_64BIT
279 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
281 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
284 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
285 #define CONFIG_SYS_MAX_NAND_DEVICE 1
287 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
288 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
289 | BR_PS_8 /* Port Size = 8 bit */ \
290 | BR_MS_FCM /* MSEL = FCM */ \
292 #if defined(CONFIG_TARGET_P1020RDB_PD)
293 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
294 | OR_FCM_PGS /* Large Page*/ \
302 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
310 #endif /* CONFIG_NAND_FSL_ELBC */
312 #define CONFIG_SYS_INIT_RAM_LOCK
313 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
314 #ifdef CONFIG_PHYS_64BIT
315 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
316 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
317 /* The assembler doesn't like typecast */
318 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
319 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
320 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
322 /* Initial L1 address */
323 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
324 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
325 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
327 /* Size of used area in RAM */
328 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
330 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
331 GENERATED_GBL_DATA_SIZE)
332 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
334 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
336 #define CONFIG_SYS_CPLD_BASE 0xffa00000
337 #ifdef CONFIG_PHYS_64BIT
338 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
340 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
342 /* CPLD config size: 1Mb */
343 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
345 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
347 #define CONFIG_SYS_PMC_BASE 0xff980000
348 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
349 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
351 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
352 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
356 #ifdef CONFIG_VSC7385_ENET
357 #define __VSCFW_ADDR "vscfw_addr=ef000000"
358 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
360 #ifdef CONFIG_PHYS_64BIT
361 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
363 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
366 #define CONFIG_SYS_VSC7385_BR_PRELIM \
367 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
368 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
369 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
370 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
372 /* The size of the VSC7385 firmware image */
373 #define CONFIG_VSC7385_IMAGE_SIZE 8192
377 * Config the L2 Cache as L2 SRAM
379 #if defined(CONFIG_SPL_BUILD)
380 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
381 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
382 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
383 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
384 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
385 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
386 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
387 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
388 #if defined(CONFIG_TARGET_P2020RDB)
389 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
391 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
393 #elif defined(CONFIG_MTD_RAW_NAND)
394 #ifdef CONFIG_TPL_BUILD
395 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
396 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
397 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
398 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
399 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
400 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
401 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
402 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
404 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
405 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
406 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
407 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
408 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
409 #endif /* CONFIG_TPL_BUILD */
413 /* Serial Port - controlled on board with jumper J8
417 #undef CONFIG_SERIAL_SOFTWARE_FIFO
418 #define CONFIG_SYS_NS16550_SERIAL
419 #define CONFIG_SYS_NS16550_REG_SIZE 1
420 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
421 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
422 #define CONFIG_NS16550_MIN_FUNCTIONS
425 #define CONFIG_SYS_BAUDRATE_TABLE \
426 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
428 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
429 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
432 #if !CONFIG_IS_ENABLED(DM_I2C)
433 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
436 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
442 #define CONFIG_RTC_PT7C4338
443 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
444 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
446 /* enable read and write access to EEPROM */
448 #if defined(CONFIG_PCI)
451 * Memory space is mapped 1-1, but I/O space must start from 0.
454 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
455 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
456 #ifdef CONFIG_PHYS_64BIT
457 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
459 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
461 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
462 #ifdef CONFIG_PHYS_64BIT
463 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
465 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
468 /* controller 1, Slot 2, tgtid 1, Base address a000 */
469 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
470 #ifdef CONFIG_PHYS_64BIT
471 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
473 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
475 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
476 #ifdef CONFIG_PHYS_64BIT
477 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
479 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
482 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
483 #endif /* CONFIG_PCI */
485 #if defined(CONFIG_TSEC_ENET)
487 #define CONFIG_TSEC1_NAME "eTSEC1"
489 #define CONFIG_TSEC2_NAME "eTSEC2"
491 #define CONFIG_TSEC3_NAME "eTSEC3"
493 #define TSEC1_PHY_ADDR 2
494 #define TSEC2_PHY_ADDR 0
495 #define TSEC3_PHY_ADDR 1
497 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
498 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
499 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
501 #define TSEC1_PHYIDX 0
502 #define TSEC2_PHYIDX 0
503 #define TSEC3_PHYIDX 0
505 #define CONFIG_ETHPRIME "eTSEC1"
507 #define CONFIG_HAS_ETH0
508 #define CONFIG_HAS_ETH1
509 #define CONFIG_HAS_ETH2
510 #endif /* CONFIG_TSEC_ENET */
515 #if defined(CONFIG_SDCARD)
516 #define CONFIG_FSL_FIXED_MMC_LOCATION
517 #elif defined(CONFIG_MTD_RAW_NAND)
518 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
519 #ifdef CONFIG_TPL_BUILD
520 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
522 #elif defined(CONFIG_SYS_RAMBOOT)
523 #define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
526 #define CONFIG_LOADS_ECHO /* echo on for serial download */
527 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
532 #define CONFIG_HAS_FSL_DR_USB
534 #if defined(CONFIG_HAS_FSL_DR_USB)
535 #ifdef CONFIG_USB_EHCI_HCD
536 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
540 #if defined(CONFIG_TARGET_P1020RDB_PD)
541 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
545 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
549 * Miscellaneous configurable options
553 * For booting Linux, the board info and command line data
554 * have to be in the first 64 MB of memory, since this is
555 * the maximum mapped by the Linux kernel during initialization.
557 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
558 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
561 * Environment Configuration
563 #define CONFIG_HOSTNAME "unknown"
564 #define CONFIG_ROOTPATH "/opt/nfsroot"
565 #define CONFIG_BOOTFILE "uImage"
566 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
569 #define __NOR_RST_CMD \
570 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
571 i2c mw 18 3 __SW_BOOT_MASK 1; reset
574 #define __SPI_RST_CMD \
575 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
576 i2c mw 18 3 __SW_BOOT_MASK 1; reset
579 #define __SD_RST_CMD \
580 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
581 i2c mw 18 3 __SW_BOOT_MASK 1; reset
583 #ifdef __SW_BOOT_NAND
584 #define __NAND_RST_CMD \
585 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
586 i2c mw 18 3 __SW_BOOT_MASK 1; reset
588 #ifdef __SW_BOOT_PCIE
589 #define __PCIE_RST_CMD \
590 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
591 i2c mw 18 3 __SW_BOOT_MASK 1; reset
594 #define CONFIG_EXTRA_ENV_SETTINGS \
596 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
597 "loadaddr=1000000\0" \
598 "bootfile=uImage\0" \
599 "tftpflash=tftpboot $loadaddr $uboot; " \
600 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
601 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
602 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
603 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
604 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
605 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
606 "consoledev=ttyS0\0" \
607 "ramdiskaddr=2000000\0" \
608 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
609 "fdtaddr=1e00000\0" \
611 "jffs2nor=mtdblock3\0" \
612 "norbootaddr=ef080000\0" \
613 "norfdtaddr=ef040000\0" \
614 "jffs2nand=mtdblock9\0" \
615 "nandbootaddr=100000\0" \
616 "nandfdtaddr=80000\0" \
617 "ramdisk_size=120000\0" \
618 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
619 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
620 __stringify(__VSCFW_ADDR)"\0" \
621 __stringify(__NOR_RST_CMD)"\0" \
622 __stringify(__SPI_RST_CMD)"\0" \
623 __stringify(__SD_RST_CMD)"\0" \
624 __stringify(__NAND_RST_CMD)"\0" \
625 __stringify(__PCIE_RST_CMD)"\0"
627 #define CONFIG_USB_FAT_BOOT \
628 "setenv bootargs root=/dev/ram rw " \
629 "console=$consoledev,$baudrate $othbootargs " \
630 "ramdisk_size=$ramdisk_size;" \
632 "fatload usb 0:2 $loadaddr $bootfile;" \
633 "fatload usb 0:2 $fdtaddr $fdtfile;" \
634 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
635 "bootm $loadaddr $ramdiskaddr $fdtaddr"
637 #define CONFIG_USB_EXT2_BOOT \
638 "setenv bootargs root=/dev/ram rw " \
639 "console=$consoledev,$baudrate $othbootargs " \
640 "ramdisk_size=$ramdisk_size;" \
642 "ext2load usb 0:4 $loadaddr $bootfile;" \
643 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
644 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
645 "bootm $loadaddr $ramdiskaddr $fdtaddr"
647 #define CONFIG_NORBOOT \
648 "setenv bootargs root=/dev/$jffs2nor rw " \
649 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
650 "bootm $norbootaddr - $norfdtaddr"
652 #endif /* __CONFIG_H */