1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * QorIQ RDB boards configuration file
13 #include <linux/stringify.h>
15 #if defined(CONFIG_TARGET_P1020MBG)
16 #define CONFIG_BOARDNAME "P1020MBG-PC"
17 #define CONFIG_VSC7385_ENET
19 #define __SW_BOOT_MASK 0x03
20 #define __SW_BOOT_NOR 0xe4
21 #define __SW_BOOT_SD 0x54
22 #define CONFIG_SYS_L2_SIZE (256 << 10)
25 #if defined(CONFIG_TARGET_P1020UTM)
26 #define CONFIG_BOARDNAME "P1020UTM-PC"
27 #define __SW_BOOT_MASK 0x03
28 #define __SW_BOOT_NOR 0xe0
29 #define __SW_BOOT_SD 0x50
30 #define CONFIG_SYS_L2_SIZE (256 << 10)
33 #if defined(CONFIG_TARGET_P1020RDB_PC)
34 #define CONFIG_BOARDNAME "P1020RDB-PC"
35 #define CONFIG_NAND_FSL_ELBC
36 #define CONFIG_VSC7385_ENET
38 #define __SW_BOOT_MASK 0x03
39 #define __SW_BOOT_NOR 0x5c
40 #define __SW_BOOT_SPI 0x1c
41 #define __SW_BOOT_SD 0x9c
42 #define __SW_BOOT_NAND 0xec
43 #define __SW_BOOT_PCIE 0x6c
44 #define CONFIG_SYS_L2_SIZE (256 << 10)
48 * P1020RDB-PD board has user selectable switches for evaluating different
49 * frequency and boot options for the P1020 device. The table that
50 * follow describe the available options. The front six binary number was in
51 * accordance with SW3[1:6].
52 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
53 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
54 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
55 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
56 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
57 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
58 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
60 #if defined(CONFIG_TARGET_P1020RDB_PD)
61 #define CONFIG_BOARDNAME "P1020RDB-PD"
62 #define CONFIG_NAND_FSL_ELBC
63 #define CONFIG_VSC7385_ENET
65 #define __SW_BOOT_MASK 0x03
66 #define __SW_BOOT_NOR 0x64
67 #define __SW_BOOT_SPI 0x34
68 #define __SW_BOOT_SD 0x24
69 #define __SW_BOOT_NAND 0x44
70 #define __SW_BOOT_PCIE 0x74
71 #define CONFIG_SYS_L2_SIZE (256 << 10)
73 * Dynamic MTD Partition support with mtdparts
77 #if defined(CONFIG_TARGET_P1021RDB)
78 #define CONFIG_BOARDNAME "P1021RDB-PC"
79 #define CONFIG_NAND_FSL_ELBC
80 #define CONFIG_VSC7385_ENET
81 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
82 addresses in the LBC */
83 #define __SW_BOOT_MASK 0x03
84 #define __SW_BOOT_NOR 0x5c
85 #define __SW_BOOT_SPI 0x1c
86 #define __SW_BOOT_SD 0x9c
87 #define __SW_BOOT_NAND 0xec
88 #define __SW_BOOT_PCIE 0x6c
89 #define CONFIG_SYS_L2_SIZE (256 << 10)
91 * Dynamic MTD Partition support with mtdparts
95 #if defined(CONFIG_TARGET_P1024RDB)
96 #define CONFIG_BOARDNAME "P1024RDB"
97 #define CONFIG_NAND_FSL_ELBC
99 #define __SW_BOOT_MASK 0xf3
100 #define __SW_BOOT_NOR 0x00
101 #define __SW_BOOT_SPI 0x08
102 #define __SW_BOOT_SD 0x04
103 #define __SW_BOOT_NAND 0x0c
104 #define CONFIG_SYS_L2_SIZE (256 << 10)
107 #if defined(CONFIG_TARGET_P1025RDB)
108 #define CONFIG_BOARDNAME "P1025RDB"
109 #define CONFIG_NAND_FSL_ELBC
112 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
113 addresses in the LBC */
114 #define __SW_BOOT_MASK 0xf3
115 #define __SW_BOOT_NOR 0x00
116 #define __SW_BOOT_SPI 0x08
117 #define __SW_BOOT_SD 0x04
118 #define __SW_BOOT_NAND 0x0c
119 #define CONFIG_SYS_L2_SIZE (256 << 10)
122 #if defined(CONFIG_TARGET_P2020RDB)
123 #define CONFIG_BOARDNAME "P2020RDB-PC"
124 #define CONFIG_NAND_FSL_ELBC
125 #define CONFIG_VSC7385_ENET
126 #define __SW_BOOT_MASK 0x03
127 #define __SW_BOOT_NOR 0xc8
128 #define __SW_BOOT_SPI 0x28
129 #define __SW_BOOT_SD 0x68 /* or 0x18 */
130 #define __SW_BOOT_NAND 0xe8
131 #define __SW_BOOT_PCIE 0xa8
132 #define CONFIG_SYS_L2_SIZE (512 << 10)
134 * Dynamic MTD Partition support with mtdparts
139 #define CONFIG_SPL_FLUSH_IMAGE
140 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
141 #define CONFIG_SPL_PAD_TO 0x20000
142 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
143 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
144 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
145 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
146 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
147 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
148 #ifdef CONFIG_SPL_BUILD
149 #define CONFIG_SPL_COMMON_INIT_DDR
153 #ifdef CONFIG_SPIFLASH
154 #define CONFIG_SPL_SPI_FLASH_MINIMAL
155 #define CONFIG_SPL_FLUSH_IMAGE
156 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
157 #define CONFIG_SPL_PAD_TO 0x20000
158 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
159 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
160 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
161 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
162 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
163 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
164 #ifdef CONFIG_SPL_BUILD
165 #define CONFIG_SPL_COMMON_INIT_DDR
169 #ifdef CONFIG_MTD_RAW_NAND
170 #ifdef CONFIG_TPL_BUILD
171 #define CONFIG_SPL_FLUSH_IMAGE
172 #define CONFIG_SPL_NAND_INIT
173 #define CONFIG_SPL_COMMON_INIT_DDR
174 #define CONFIG_SPL_MAX_SIZE (128 << 10)
175 #define CONFIG_TPL_TEXT_BASE 0xf8f81000
176 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
177 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
178 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
179 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
180 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
181 #elif defined(CONFIG_SPL_BUILD)
182 #define CONFIG_SPL_INIT_MINIMAL
183 #define CONFIG_SPL_FLUSH_IMAGE
184 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
185 #define CONFIG_SPL_MAX_SIZE 4096
186 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
187 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
188 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
189 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
190 #endif /* not CONFIG_TPL_BUILD */
192 #define CONFIG_SPL_PAD_TO 0x20000
193 #define CONFIG_TPL_PAD_TO 0x20000
194 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
197 #ifndef CONFIG_RESET_VECTOR_ADDRESS
198 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
201 #ifndef CONFIG_SYS_MONITOR_BASE
202 #ifdef CONFIG_TPL_BUILD
203 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
204 #elif defined(CONFIG_SPL_BUILD)
205 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
207 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
211 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
212 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
213 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
215 #define CONFIG_ENV_OVERWRITE
217 #define CONFIG_SYS_SATA_MAX_DEVICE 2
220 #if defined(CONFIG_TARGET_P2020RDB)
221 #define CONFIG_SYS_CLK_FREQ 100000000
223 #define CONFIG_SYS_CLK_FREQ 66666666
225 #define CONFIG_DDR_CLK_FREQ 66666666
227 #define CONFIG_HWCONFIG
229 * These can be toggled for performance analysis, otherwise use default.
231 #define CONFIG_L2_CACHE
234 #define CONFIG_ENABLE_36BIT_PHYS
236 #define CONFIG_SYS_CCSRBAR 0xffe00000
237 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
239 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
241 #ifdef CONFIG_SPL_BUILD
242 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
246 #define CONFIG_SYS_DDR_RAW_TIMING
247 #define CONFIG_DDR_SPD
248 #define CONFIG_SYS_SPD_BUS_NUM 1
249 #define SPD_EEPROM_ADDRESS 0x52
251 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
252 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
253 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
255 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
256 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
258 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
259 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
260 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
262 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
264 /* Default settings for DDR3 */
265 #ifndef CONFIG_TARGET_P2020RDB
266 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
267 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
268 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
269 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
270 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
271 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
273 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
274 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
275 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
276 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
278 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
279 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
280 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
281 #define CONFIG_SYS_DDR_RCW_1 0x00000000
282 #define CONFIG_SYS_DDR_RCW_2 0x00000000
283 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
284 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
285 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
286 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
288 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
289 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
290 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
291 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
292 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
293 #define CONFIG_SYS_DDR_MODE_1 0x40461520
294 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
295 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
301 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
302 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
303 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
304 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
306 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
307 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
308 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
309 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
310 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
311 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
312 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
316 * Local Bus Definitions
318 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
319 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
320 #define CONFIG_SYS_FLASH_BASE 0xec000000
321 #elif defined(CONFIG_TARGET_P1020UTM)
322 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
323 #define CONFIG_SYS_FLASH_BASE 0xee000000
325 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
326 #define CONFIG_SYS_FLASH_BASE 0xef000000
329 #ifdef CONFIG_PHYS_64BIT
330 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
332 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
335 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
338 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
340 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
341 #define CONFIG_SYS_FLASH_QUIET_TEST
342 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
344 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
346 #undef CONFIG_SYS_FLASH_CHECKSUM
347 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
348 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
350 #define CONFIG_SYS_FLASH_EMPTY_INFO
353 #ifdef CONFIG_NAND_FSL_ELBC
354 #define CONFIG_SYS_NAND_BASE 0xff800000
355 #ifdef CONFIG_PHYS_64BIT
356 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
358 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
361 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
362 #define CONFIG_SYS_MAX_NAND_DEVICE 1
363 #if defined(CONFIG_TARGET_P1020RDB_PD)
364 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
366 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
369 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
370 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
371 | BR_PS_8 /* Port Size = 8 bit */ \
372 | BR_MS_FCM /* MSEL = FCM */ \
374 #if defined(CONFIG_TARGET_P1020RDB_PD)
375 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
376 | OR_FCM_PGS /* Large Page*/ \
384 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
392 #endif /* CONFIG_NAND_FSL_ELBC */
394 #define CONFIG_SYS_INIT_RAM_LOCK
395 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
396 #ifdef CONFIG_PHYS_64BIT
397 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
398 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
399 /* The assembler doesn't like typecast */
400 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
401 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
402 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
404 /* Initial L1 address */
405 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
406 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
407 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
409 /* Size of used area in RAM */
410 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
412 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
413 GENERATED_GBL_DATA_SIZE)
414 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
416 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
417 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
419 #define CONFIG_SYS_CPLD_BASE 0xffa00000
420 #ifdef CONFIG_PHYS_64BIT
421 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
423 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
425 /* CPLD config size: 1Mb */
426 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
428 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
430 #define CONFIG_SYS_PMC_BASE 0xff980000
431 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
432 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
434 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
435 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
438 #ifdef CONFIG_MTD_RAW_NAND
439 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
440 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
441 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
442 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
444 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
445 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
446 #ifdef CONFIG_NAND_FSL_ELBC
447 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
448 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
451 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
452 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
455 #ifdef CONFIG_VSC7385_ENET
456 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
458 #ifdef CONFIG_PHYS_64BIT
459 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
461 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
464 #define CONFIG_SYS_VSC7385_BR_PRELIM \
465 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
466 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
467 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
468 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
470 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
471 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
473 /* The size of the VSC7385 firmware image */
474 #define CONFIG_VSC7385_IMAGE_SIZE 8192
478 * Config the L2 Cache as L2 SRAM
480 #if defined(CONFIG_SPL_BUILD)
481 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
482 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
483 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
484 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
485 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
486 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
487 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
488 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
489 #if defined(CONFIG_TARGET_P2020RDB)
490 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
492 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
494 #elif defined(CONFIG_MTD_RAW_NAND)
495 #ifdef CONFIG_TPL_BUILD
496 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
497 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
498 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
499 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
500 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
501 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
502 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
503 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
505 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
506 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
507 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
508 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
509 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
510 #endif /* CONFIG_TPL_BUILD */
514 /* Serial Port - controlled on board with jumper J8
518 #undef CONFIG_SERIAL_SOFTWARE_FIFO
519 #define CONFIG_SYS_NS16550_SERIAL
520 #define CONFIG_SYS_NS16550_REG_SIZE 1
521 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
522 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
523 #define CONFIG_NS16550_MIN_FUNCTIONS
526 #define CONFIG_SYS_BAUDRATE_TABLE \
527 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
529 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
530 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
533 #ifndef CONFIG_DM_I2C
534 #define CONFIG_SYS_I2C
535 #define CONFIG_SYS_FSL_I2C_SPEED 400000
536 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
537 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
538 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
539 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
540 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
541 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
543 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
544 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
547 #define CONFIG_SYS_I2C_FSL
548 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
549 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
554 #undef CONFIG_ID_EEPROM
556 #define CONFIG_RTC_PT7C4338
557 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
558 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
560 /* enable read and write access to EEPROM */
561 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
562 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
563 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
565 #if defined(CONFIG_PCI)
568 * Memory space is mapped 1-1, but I/O space must start from 0.
571 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
572 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
573 #ifdef CONFIG_PHYS_64BIT
574 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
576 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
578 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
579 #ifdef CONFIG_PHYS_64BIT
580 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
582 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
585 /* controller 1, Slot 2, tgtid 1, Base address a000 */
586 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
587 #ifdef CONFIG_PHYS_64BIT
588 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
590 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
592 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
593 #ifdef CONFIG_PHYS_64BIT
594 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
596 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
599 #if !defined(CONFIG_DM_PCI)
600 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
601 #define CONFIG_PCI_INDIRECT_BRIDGE
602 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
603 #ifdef CONFIG_PHYS_64BIT
604 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
606 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
608 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
609 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
610 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
612 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
613 #ifdef CONFIG_PHYS_64BIT
614 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
616 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
618 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
619 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
620 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
623 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
624 #endif /* CONFIG_PCI */
626 #if defined(CONFIG_TSEC_ENET)
628 #define CONFIG_TSEC1_NAME "eTSEC1"
630 #define CONFIG_TSEC2_NAME "eTSEC2"
632 #define CONFIG_TSEC3_NAME "eTSEC3"
634 #define TSEC1_PHY_ADDR 2
635 #define TSEC2_PHY_ADDR 0
636 #define TSEC3_PHY_ADDR 1
638 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
639 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
640 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
642 #define TSEC1_PHYIDX 0
643 #define TSEC2_PHYIDX 0
644 #define TSEC3_PHYIDX 0
646 #define CONFIG_ETHPRIME "eTSEC1"
648 #define CONFIG_HAS_ETH0
649 #define CONFIG_HAS_ETH1
650 #define CONFIG_HAS_ETH2
651 #endif /* CONFIG_TSEC_ENET */
654 /* QE microcode/firmware address */
655 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
656 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
657 #endif /* CONFIG_QE */
659 #ifdef CONFIG_TARGET_P1025RDB
661 * QE UEC ethernet configuration
663 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
665 #undef CONFIG_UEC_ETH
666 #define CONFIG_PHY_MODE_NEED_CHANGE
668 #define CONFIG_UEC_ETH1 /* ETH1 */
669 #define CONFIG_HAS_ETH0
671 #ifdef CONFIG_UEC_ETH1
672 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
673 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
674 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
675 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
676 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
677 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
678 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
679 #endif /* CONFIG_UEC_ETH1 */
681 #define CONFIG_UEC_ETH5 /* ETH5 */
682 #define CONFIG_HAS_ETH1
684 #ifdef CONFIG_UEC_ETH5
685 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
686 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
687 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
688 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
689 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
690 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
691 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
692 #endif /* CONFIG_UEC_ETH5 */
693 #endif /* CONFIG_TARGET_P1025RDB */
698 #if defined(CONFIG_SDCARD)
699 #define CONFIG_FSL_FIXED_MMC_LOCATION
700 #define CONFIG_SYS_MMC_ENV_DEV 0
701 #elif defined(CONFIG_MTD_RAW_NAND)
702 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
703 #ifdef CONFIG_TPL_BUILD
704 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
706 #elif defined(CONFIG_SYS_RAMBOOT)
707 #define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
710 #define CONFIG_LOADS_ECHO /* echo on for serial download */
711 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
716 #define CONFIG_HAS_FSL_DR_USB
718 #if defined(CONFIG_HAS_FSL_DR_USB)
719 #ifdef CONFIG_USB_EHCI_HCD
720 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
721 #define CONFIG_USB_EHCI_FSL
725 #if defined(CONFIG_TARGET_P1020RDB_PD)
726 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
730 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
733 #undef CONFIG_WATCHDOG /* watchdog disabled */
736 * Miscellaneous configurable options
738 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
741 * For booting Linux, the board info and command line data
742 * have to be in the first 64 MB of memory, since this is
743 * the maximum mapped by the Linux kernel during initialization.
745 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
746 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
748 #if defined(CONFIG_CMD_KGDB)
749 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
753 * Environment Configuration
755 #define CONFIG_HOSTNAME "unknown"
756 #define CONFIG_ROOTPATH "/opt/nfsroot"
757 #define CONFIG_BOOTFILE "uImage"
758 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
760 /* default location for tftp and bootm */
761 #define CONFIG_LOADADDR 1000000
764 #define __NOR_RST_CMD \
765 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
766 i2c mw 18 3 __SW_BOOT_MASK 1; reset
769 #define __SPI_RST_CMD \
770 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
771 i2c mw 18 3 __SW_BOOT_MASK 1; reset
774 #define __SD_RST_CMD \
775 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
776 i2c mw 18 3 __SW_BOOT_MASK 1; reset
778 #ifdef __SW_BOOT_NAND
779 #define __NAND_RST_CMD \
780 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
781 i2c mw 18 3 __SW_BOOT_MASK 1; reset
783 #ifdef __SW_BOOT_PCIE
784 #define __PCIE_RST_CMD \
785 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
786 i2c mw 18 3 __SW_BOOT_MASK 1; reset
789 #define CONFIG_EXTRA_ENV_SETTINGS \
791 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
792 "loadaddr=1000000\0" \
793 "bootfile=uImage\0" \
794 "tftpflash=tftpboot $loadaddr $uboot; " \
795 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
796 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
797 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
798 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
799 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
800 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
801 "consoledev=ttyS0\0" \
802 "ramdiskaddr=2000000\0" \
803 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
804 "fdtaddr=1e00000\0" \
806 "jffs2nor=mtdblock3\0" \
807 "norbootaddr=ef080000\0" \
808 "norfdtaddr=ef040000\0" \
809 "jffs2nand=mtdblock9\0" \
810 "nandbootaddr=100000\0" \
811 "nandfdtaddr=80000\0" \
812 "ramdisk_size=120000\0" \
813 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
814 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
815 __stringify(__NOR_RST_CMD)"\0" \
816 __stringify(__SPI_RST_CMD)"\0" \
817 __stringify(__SD_RST_CMD)"\0" \
818 __stringify(__NAND_RST_CMD)"\0" \
819 __stringify(__PCIE_RST_CMD)"\0"
821 #define CONFIG_NFSBOOTCOMMAND \
822 "setenv bootargs root=/dev/nfs rw " \
823 "nfsroot=$serverip:$rootpath " \
824 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
825 "console=$consoledev,$baudrate $othbootargs;" \
826 "tftp $loadaddr $bootfile;" \
827 "tftp $fdtaddr $fdtfile;" \
828 "bootm $loadaddr - $fdtaddr"
830 #define CONFIG_HDBOOT \
831 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
832 "console=$consoledev,$baudrate $othbootargs;" \
834 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
835 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
836 "bootm $loadaddr - $fdtaddr"
838 #define CONFIG_USB_FAT_BOOT \
839 "setenv bootargs root=/dev/ram rw " \
840 "console=$consoledev,$baudrate $othbootargs " \
841 "ramdisk_size=$ramdisk_size;" \
843 "fatload usb 0:2 $loadaddr $bootfile;" \
844 "fatload usb 0:2 $fdtaddr $fdtfile;" \
845 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
846 "bootm $loadaddr $ramdiskaddr $fdtaddr"
848 #define CONFIG_USB_EXT2_BOOT \
849 "setenv bootargs root=/dev/ram rw " \
850 "console=$consoledev,$baudrate $othbootargs " \
851 "ramdisk_size=$ramdisk_size;" \
853 "ext2load usb 0:4 $loadaddr $bootfile;" \
854 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
855 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
856 "bootm $loadaddr $ramdiskaddr $fdtaddr"
858 #define CONFIG_NORBOOT \
859 "setenv bootargs root=/dev/$jffs2nor rw " \
860 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
861 "bootm $norbootaddr - $norfdtaddr"
863 #define CONFIG_RAMBOOTCOMMAND \
864 "setenv bootargs root=/dev/ram rw " \
865 "console=$consoledev,$baudrate $othbootargs " \
866 "ramdisk_size=$ramdisk_size;" \
867 "tftp $ramdiskaddr $ramdiskfile;" \
868 "tftp $loadaddr $bootfile;" \
869 "tftp $fdtaddr $fdtfile;" \
870 "bootm $loadaddr $ramdiskaddr $fdtaddr"
872 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
874 #endif /* __CONFIG_H */