1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * QorIQ RDB boards configuration file
13 #include <linux/stringify.h>
15 #if defined(CONFIG_TARGET_P1020RDB_PC)
16 #define CONFIG_BOARDNAME "P1020RDB-PC"
17 #define CONFIG_VSC7385_ENET
19 #define __SW_BOOT_MASK 0x03
20 #define __SW_BOOT_NOR 0x5c
21 #define __SW_BOOT_SPI 0x1c
22 #define __SW_BOOT_SD 0x9c
23 #define __SW_BOOT_NAND 0xec
24 #define __SW_BOOT_PCIE 0x6c
25 #define CONFIG_SYS_L2_SIZE (256 << 10)
29 * P1020RDB-PD board has user selectable switches for evaluating different
30 * frequency and boot options for the P1020 device. The table that
31 * follow describe the available options. The front six binary number was in
32 * accordance with SW3[1:6].
33 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
34 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
35 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
36 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
37 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
38 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
39 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
41 #if defined(CONFIG_TARGET_P1020RDB_PD)
42 #define CONFIG_BOARDNAME "P1020RDB-PD"
43 #define CONFIG_VSC7385_ENET
45 #define __SW_BOOT_MASK 0x03
46 #define __SW_BOOT_NOR 0x64
47 #define __SW_BOOT_SPI 0x34
48 #define __SW_BOOT_SD 0x24
49 #define __SW_BOOT_NAND 0x44
50 #define __SW_BOOT_PCIE 0x74
51 #define CONFIG_SYS_L2_SIZE (256 << 10)
53 * Dynamic MTD Partition support with mtdparts
57 #if defined(CONFIG_TARGET_P2020RDB)
58 #define CONFIG_BOARDNAME "P2020RDB-PC"
59 #define CONFIG_VSC7385_ENET
60 #define __SW_BOOT_MASK 0x03
61 #define __SW_BOOT_NOR 0xc8
62 #define __SW_BOOT_SPI 0x28
63 #define __SW_BOOT_SD 0x68 /* or 0x18 */
64 #define __SW_BOOT_NAND 0xe8
65 #define __SW_BOOT_PCIE 0xa8
66 #define CONFIG_SYS_L2_SIZE (512 << 10)
68 * Dynamic MTD Partition support with mtdparts
73 #define CONFIG_SPL_FLUSH_IMAGE
74 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
75 #define CONFIG_SPL_PAD_TO 0x20000
76 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
77 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
78 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
79 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
80 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
81 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
82 #ifdef CONFIG_SPL_BUILD
83 #define CONFIG_SPL_COMMON_INIT_DDR
85 #elif defined(CONFIG_SPIFLASH)
86 #define CONFIG_SPL_SPI_FLASH_MINIMAL
87 #define CONFIG_SPL_FLUSH_IMAGE
88 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
89 #define CONFIG_SPL_PAD_TO 0x20000
90 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
91 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
92 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
93 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
94 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
95 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
96 #ifdef CONFIG_SPL_BUILD
97 #define CONFIG_SPL_COMMON_INIT_DDR
99 #elif defined(CONFIG_MTD_RAW_NAND)
100 #ifdef CONFIG_TPL_BUILD
101 #define CONFIG_SPL_FLUSH_IMAGE
102 #define CONFIG_SPL_NAND_INIT
103 #define CONFIG_SPL_COMMON_INIT_DDR
104 #define CONFIG_SPL_MAX_SIZE (128 << 10)
105 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
106 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
107 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
108 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
109 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
110 #elif defined(CONFIG_SPL_BUILD)
111 #define CONFIG_SPL_INIT_MINIMAL
112 #define CONFIG_SPL_FLUSH_IMAGE
113 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
114 #define CONFIG_SPL_MAX_SIZE 4096
115 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
116 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
117 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
118 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
119 #endif /* not CONFIG_TPL_BUILD */
121 #define CONFIG_SPL_PAD_TO 0x20000
122 #define CONFIG_TPL_PAD_TO 0x20000
123 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
126 #ifndef CONFIG_RESET_VECTOR_ADDRESS
127 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
130 #ifndef CONFIG_SYS_MONITOR_BASE
131 #ifdef CONFIG_TPL_BUILD
132 #define CONFIG_SYS_MONITOR_BASE 0xf8f81000
133 #elif defined(CONFIG_SPL_BUILD)
134 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
136 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
140 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
141 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
143 #define CONFIG_SYS_SATA_MAX_DEVICE 2
146 #if defined(CONFIG_TARGET_P2020RDB)
147 #define CONFIG_SYS_CLK_FREQ 100000000
149 #define CONFIG_SYS_CLK_FREQ 66666666
152 #define CONFIG_HWCONFIG
154 * These can be toggled for performance analysis, otherwise use default.
156 #define CONFIG_L2_CACHE
159 #define CONFIG_ENABLE_36BIT_PHYS
161 #define CONFIG_SYS_CCSRBAR 0xffe00000
162 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
164 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
166 #ifdef CONFIG_SPL_BUILD
167 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
171 #define CONFIG_SYS_DDR_RAW_TIMING
172 #define CONFIG_SYS_SPD_BUS_NUM 1
173 #define SPD_EEPROM_ADDRESS 0x52
175 #if defined(CONFIG_TARGET_P1020RDB_PD)
176 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
177 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
179 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
180 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
182 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
183 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
184 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
186 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
188 /* Default settings for DDR3 */
189 #ifndef CONFIG_TARGET_P2020RDB
190 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
191 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
192 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
193 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
194 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
195 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
197 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
198 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
199 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
200 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
202 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
203 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
204 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
205 #define CONFIG_SYS_DDR_RCW_1 0x00000000
206 #define CONFIG_SYS_DDR_RCW_2 0x00000000
207 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
208 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
209 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
210 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
212 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
213 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
214 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
215 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
216 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
217 #define CONFIG_SYS_DDR_MODE_1 0x40461520
218 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
219 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
225 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
226 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
227 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
228 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
230 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
231 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
232 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
233 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
234 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
235 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
236 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
240 * Local Bus Definitions
242 #if defined(CONFIG_TARGET_P1020RDB_PD)
243 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
244 #define CONFIG_SYS_FLASH_BASE 0xec000000
246 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
247 #define CONFIG_SYS_FLASH_BASE 0xef000000
250 #ifdef CONFIG_PHYS_64BIT
251 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
253 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
256 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
259 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
261 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
262 #define CONFIG_SYS_FLASH_QUIET_TEST
263 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
265 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
267 #undef CONFIG_SYS_FLASH_CHECKSUM
268 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
269 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
271 #define CONFIG_SYS_FLASH_EMPTY_INFO
274 #ifdef CONFIG_NAND_FSL_ELBC
275 #define CONFIG_SYS_NAND_BASE 0xff800000
276 #ifdef CONFIG_PHYS_64BIT
277 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
279 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
282 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
283 #define CONFIG_SYS_MAX_NAND_DEVICE 1
285 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
286 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
287 | BR_PS_8 /* Port Size = 8 bit */ \
288 | BR_MS_FCM /* MSEL = FCM */ \
290 #if defined(CONFIG_TARGET_P1020RDB_PD)
291 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
292 | OR_FCM_PGS /* Large Page*/ \
300 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
308 #endif /* CONFIG_NAND_FSL_ELBC */
310 #define CONFIG_SYS_INIT_RAM_LOCK
311 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
312 #ifdef CONFIG_PHYS_64BIT
313 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
314 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
315 /* The assembler doesn't like typecast */
316 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
317 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
318 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
320 /* Initial L1 address */
321 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
322 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
323 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
325 /* Size of used area in RAM */
326 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
328 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
329 GENERATED_GBL_DATA_SIZE)
330 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
332 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
334 #define CONFIG_SYS_CPLD_BASE 0xffa00000
335 #ifdef CONFIG_PHYS_64BIT
336 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
338 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
340 /* CPLD config size: 1Mb */
341 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
343 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
345 #define CONFIG_SYS_PMC_BASE 0xff980000
346 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
347 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
349 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
350 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
354 #ifdef CONFIG_VSC7385_ENET
355 #define __VSCFW_ADDR "vscfw_addr=ef000000"
356 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
358 #ifdef CONFIG_PHYS_64BIT
359 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
361 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
364 #define CONFIG_SYS_VSC7385_BR_PRELIM \
365 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
366 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
367 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
368 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
370 /* The size of the VSC7385 firmware image */
371 #define CONFIG_VSC7385_IMAGE_SIZE 8192
375 * Config the L2 Cache as L2 SRAM
377 #if defined(CONFIG_SPL_BUILD)
378 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
379 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
380 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
381 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
382 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
383 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
384 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
385 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
386 #if defined(CONFIG_TARGET_P2020RDB)
387 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
389 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
391 #elif defined(CONFIG_MTD_RAW_NAND)
392 #ifdef CONFIG_TPL_BUILD
393 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
394 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
395 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
396 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
397 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
398 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
399 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
400 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
402 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
403 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
404 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
405 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
406 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
407 #endif /* CONFIG_TPL_BUILD */
411 /* Serial Port - controlled on board with jumper J8
415 #undef CONFIG_SERIAL_SOFTWARE_FIFO
416 #define CONFIG_SYS_NS16550_SERIAL
417 #define CONFIG_SYS_NS16550_REG_SIZE 1
418 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
419 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
420 #define CONFIG_NS16550_MIN_FUNCTIONS
423 #define CONFIG_SYS_BAUDRATE_TABLE \
424 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
426 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
427 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
430 #if !CONFIG_IS_ENABLED(DM_I2C)
431 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
434 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
440 #define CONFIG_RTC_PT7C4338
441 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
442 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
444 /* enable read and write access to EEPROM */
446 #if defined(CONFIG_PCI)
449 * Memory space is mapped 1-1, but I/O space must start from 0.
452 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
453 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
454 #ifdef CONFIG_PHYS_64BIT
455 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
457 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
459 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
460 #ifdef CONFIG_PHYS_64BIT
461 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
463 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
466 /* controller 1, Slot 2, tgtid 1, Base address a000 */
467 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
468 #ifdef CONFIG_PHYS_64BIT
469 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
471 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
473 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
474 #ifdef CONFIG_PHYS_64BIT
475 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
477 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
480 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
481 #endif /* CONFIG_PCI */
483 #if defined(CONFIG_TSEC_ENET)
485 #define CONFIG_TSEC1_NAME "eTSEC1"
487 #define CONFIG_TSEC2_NAME "eTSEC2"
489 #define CONFIG_TSEC3_NAME "eTSEC3"
491 #define TSEC1_PHY_ADDR 2
492 #define TSEC2_PHY_ADDR 0
493 #define TSEC3_PHY_ADDR 1
495 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
496 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
497 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
499 #define TSEC1_PHYIDX 0
500 #define TSEC2_PHYIDX 0
501 #define TSEC3_PHYIDX 0
503 #define CONFIG_ETHPRIME "eTSEC1"
505 #define CONFIG_HAS_ETH0
506 #define CONFIG_HAS_ETH1
507 #define CONFIG_HAS_ETH2
508 #endif /* CONFIG_TSEC_ENET */
513 #if defined(CONFIG_SDCARD)
514 #define CONFIG_FSL_FIXED_MMC_LOCATION
515 #elif defined(CONFIG_MTD_RAW_NAND)
516 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
517 #ifdef CONFIG_TPL_BUILD
518 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
520 #elif defined(CONFIG_SYS_RAMBOOT)
521 #define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
524 #define CONFIG_LOADS_ECHO /* echo on for serial download */
525 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
530 #define CONFIG_HAS_FSL_DR_USB
532 #if defined(CONFIG_HAS_FSL_DR_USB)
533 #ifdef CONFIG_USB_EHCI_HCD
534 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
538 #if defined(CONFIG_TARGET_P1020RDB_PD)
539 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
543 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
547 * Miscellaneous configurable options
551 * For booting Linux, the board info and command line data
552 * have to be in the first 64 MB of memory, since this is
553 * the maximum mapped by the Linux kernel during initialization.
555 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
556 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
559 * Environment Configuration
561 #define CONFIG_HOSTNAME "unknown"
562 #define CONFIG_ROOTPATH "/opt/nfsroot"
563 #define CONFIG_BOOTFILE "uImage"
564 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
567 #define __NOR_RST_CMD \
568 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
569 i2c mw 18 3 __SW_BOOT_MASK 1; reset
572 #define __SPI_RST_CMD \
573 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
574 i2c mw 18 3 __SW_BOOT_MASK 1; reset
577 #define __SD_RST_CMD \
578 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
579 i2c mw 18 3 __SW_BOOT_MASK 1; reset
581 #ifdef __SW_BOOT_NAND
582 #define __NAND_RST_CMD \
583 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
584 i2c mw 18 3 __SW_BOOT_MASK 1; reset
586 #ifdef __SW_BOOT_PCIE
587 #define __PCIE_RST_CMD \
588 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
589 i2c mw 18 3 __SW_BOOT_MASK 1; reset
592 #define CONFIG_EXTRA_ENV_SETTINGS \
594 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
595 "loadaddr=1000000\0" \
596 "bootfile=uImage\0" \
597 "tftpflash=tftpboot $loadaddr $uboot; " \
598 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
599 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
600 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
601 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
602 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
603 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
604 "consoledev=ttyS0\0" \
605 "ramdiskaddr=2000000\0" \
606 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
607 "fdtaddr=1e00000\0" \
609 "jffs2nor=mtdblock3\0" \
610 "norbootaddr=ef080000\0" \
611 "norfdtaddr=ef040000\0" \
612 "jffs2nand=mtdblock9\0" \
613 "nandbootaddr=100000\0" \
614 "nandfdtaddr=80000\0" \
615 "ramdisk_size=120000\0" \
616 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
617 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
618 __stringify(__VSCFW_ADDR)"\0" \
619 __stringify(__NOR_RST_CMD)"\0" \
620 __stringify(__SPI_RST_CMD)"\0" \
621 __stringify(__SD_RST_CMD)"\0" \
622 __stringify(__NAND_RST_CMD)"\0" \
623 __stringify(__PCIE_RST_CMD)"\0"
625 #define CONFIG_USB_FAT_BOOT \
626 "setenv bootargs root=/dev/ram rw " \
627 "console=$consoledev,$baudrate $othbootargs " \
628 "ramdisk_size=$ramdisk_size;" \
630 "fatload usb 0:2 $loadaddr $bootfile;" \
631 "fatload usb 0:2 $fdtaddr $fdtfile;" \
632 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
633 "bootm $loadaddr $ramdiskaddr $fdtaddr"
635 #define CONFIG_USB_EXT2_BOOT \
636 "setenv bootargs root=/dev/ram rw " \
637 "console=$consoledev,$baudrate $othbootargs " \
638 "ramdisk_size=$ramdisk_size;" \
640 "ext2load usb 0:4 $loadaddr $bootfile;" \
641 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
642 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
643 "bootm $loadaddr $ramdiskaddr $fdtaddr"
645 #define CONFIG_NORBOOT \
646 "setenv bootargs root=/dev/$jffs2nor rw " \
647 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
648 "bootm $norbootaddr - $norfdtaddr"
650 #endif /* __CONFIG_H */