1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * QorIQ RDB boards configuration file
13 #include <linux/stringify.h>
15 #if defined(CONFIG_TARGET_P1020RDB_PC)
16 #define CONFIG_VSC7385_ENET
18 #define __SW_BOOT_MASK 0x03
19 #define __SW_BOOT_NOR 0x5c
20 #define __SW_BOOT_SPI 0x1c
21 #define __SW_BOOT_SD 0x9c
22 #define __SW_BOOT_NAND 0xec
23 #define __SW_BOOT_PCIE 0x6c
24 #define __SW_NOR_BANK_MASK 0xfd
25 #define __SW_NOR_BANK_UP 0x00
26 #define __SW_NOR_BANK_LO 0x02
27 #define CONFIG_SYS_L2_SIZE (256 << 10)
31 * P1020RDB-PD board has user selectable switches for evaluating different
32 * frequency and boot options for the P1020 device. The table that
33 * follow describe the available options. The front six binary number was in
34 * accordance with SW3[1:6].
35 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
36 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
37 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
38 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
39 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
40 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
41 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
43 #if defined(CONFIG_TARGET_P1020RDB_PD)
44 #define CONFIG_VSC7385_ENET
46 #define __SW_BOOT_MASK 0x03
47 #define __SW_BOOT_NOR 0x64
48 #define __SW_BOOT_SPI 0x34
49 #define __SW_BOOT_SD 0x24
50 #define __SW_BOOT_NAND 0x44
51 #define __SW_BOOT_PCIE 0x74
52 #define __SW_NOR_BANK_MASK 0xfd
53 #define __SW_NOR_BANK_UP 0x00
54 #define __SW_NOR_BANK_LO 0x02
55 #define CONFIG_SYS_L2_SIZE (256 << 10)
57 * Dynamic MTD Partition support with mtdparts
61 #if defined(CONFIG_TARGET_P2020RDB)
62 #define CONFIG_VSC7385_ENET
63 #define __SW_BOOT_MASK 0x03
64 #define __SW_BOOT_NOR 0xc8
65 #define __SW_BOOT_SPI 0x28
66 #define __SW_BOOT_SD 0x68
67 #define __SW_BOOT_SD2 0x18
68 #define __SW_BOOT_NAND 0xe8
69 #define __SW_BOOT_PCIE 0xa8
70 #define __SW_NOR_BANK_MASK 0xfd
71 #define __SW_NOR_BANK_UP 0x00
72 #define __SW_NOR_BANK_LO 0x02
73 #define CONFIG_SYS_L2_SIZE (512 << 10)
75 * Dynamic MTD Partition support with mtdparts
80 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
81 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
82 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
83 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
84 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
85 #elif defined(CONFIG_SPIFLASH)
86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
87 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
88 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
89 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
90 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
91 #elif defined(CONFIG_MTD_RAW_NAND)
92 #ifdef CONFIG_TPL_BUILD
93 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
94 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
95 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
96 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
97 #elif defined(CONFIG_SPL_BUILD)
98 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
99 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
100 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
102 #ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
103 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
105 #endif /* not CONFIG_TPL_BUILD */
108 #ifndef CONFIG_RESET_VECTOR_ADDRESS
109 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
112 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
113 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
117 #define CONFIG_HWCONFIG
119 * These can be toggled for performance analysis, otherwise use default.
121 #define CONFIG_L2_CACHE
123 #define CONFIG_ENABLE_36BIT_PHYS
125 #define CONFIG_SYS_CCSRBAR 0xffe00000
126 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
129 #define CONFIG_SYS_DDR_RAW_TIMING
130 #define CONFIG_SYS_SPD_BUS_NUM 1
131 #define SPD_EEPROM_ADDRESS 0x52
133 #if defined(CONFIG_TARGET_P1020RDB_PD)
134 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
136 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
138 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
139 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
140 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
142 /* Default settings for DDR3 */
143 #ifndef CONFIG_TARGET_P2020RDB
144 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
145 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
146 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
147 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
148 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
149 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
151 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
152 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
153 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
154 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
156 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
157 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
158 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
159 #define CONFIG_SYS_DDR_RCW_1 0x00000000
160 #define CONFIG_SYS_DDR_RCW_2 0x00000000
161 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
162 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
163 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
164 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
166 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
167 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
168 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
169 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
170 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
171 #define CONFIG_SYS_DDR_MODE_1 0x40461520
172 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
173 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
179 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
180 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
181 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
182 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
184 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
185 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
186 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
187 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
188 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
189 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
190 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
194 * Local Bus Definitions
196 #if defined(CONFIG_TARGET_P1020RDB_PD)
197 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
198 #define CONFIG_SYS_FLASH_BASE 0xec000000
200 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
201 #define CONFIG_SYS_FLASH_BASE 0xef000000
204 #ifdef CONFIG_PHYS_64BIT
205 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
207 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
210 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
213 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
215 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
216 #define CONFIG_SYS_FLASH_QUIET_TEST
217 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
219 #undef CONFIG_SYS_FLASH_CHECKSUM
220 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
221 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
223 #define CONFIG_SYS_FLASH_EMPTY_INFO
226 #ifdef CONFIG_NAND_FSL_ELBC
227 #define CONFIG_SYS_NAND_BASE 0xff800000
228 #ifdef CONFIG_PHYS_64BIT
229 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
231 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
234 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
235 #define CONFIG_SYS_MAX_NAND_DEVICE 1
237 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
238 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
239 | BR_PS_8 /* Port Size = 8 bit */ \
240 | BR_MS_FCM /* MSEL = FCM */ \
242 #if defined(CONFIG_TARGET_P1020RDB_PD)
243 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
244 | OR_FCM_PGS /* Large Page*/ \
252 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
260 #endif /* CONFIG_NAND_FSL_ELBC */
262 #define CONFIG_SYS_INIT_RAM_LOCK
263 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
264 #ifdef CONFIG_PHYS_64BIT
265 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
266 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
267 /* The assembler doesn't like typecast */
268 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
269 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
270 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
272 /* Initial L1 address */
273 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
274 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
275 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
277 /* Size of used area in RAM */
278 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
280 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
282 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
284 #define CONFIG_SYS_CPLD_BASE 0xffa00000
285 #ifdef CONFIG_PHYS_64BIT
286 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
288 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
290 /* CPLD config size: 1Mb */
292 #define CONFIG_SYS_PMC_BASE 0xff980000
293 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
294 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
296 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
297 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
301 #ifdef CONFIG_VSC7385_ENET
302 #define __VSCFW_ADDR "vscfw_addr=ef000000\0"
303 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
305 #ifdef CONFIG_PHYS_64BIT
306 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
308 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
311 #define CONFIG_SYS_VSC7385_BR_PRELIM \
312 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
313 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
314 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
315 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
317 /* The size of the VSC7385 firmware image */
318 #define CONFIG_VSC7385_IMAGE_SIZE 8192
322 #define __VSCFW_ADDR ""
326 * Config the L2 Cache as L2 SRAM
328 #if defined(CONFIG_SPL_BUILD)
329 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
330 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
331 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
332 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
333 #elif defined(CONFIG_MTD_RAW_NAND)
334 #ifdef CONFIG_TPL_BUILD
335 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
336 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
337 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
339 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
340 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
341 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
342 #endif /* CONFIG_TPL_BUILD */
346 /* Serial Port - controlled on board with jumper J8
350 #undef CONFIG_SERIAL_SOFTWARE_FIFO
351 #define CONFIG_SYS_NS16550_SERIAL
352 #define CONFIG_SYS_NS16550_REG_SIZE 1
353 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
354 #if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)
355 #define CONFIG_NS16550_MIN_FUNCTIONS
358 #define CONFIG_SYS_BAUDRATE_TABLE \
359 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
361 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
362 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
365 #if !CONFIG_IS_ENABLED(DM_I2C)
366 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
369 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
375 #define CONFIG_RTC_PT7C4338
376 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
377 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
379 /* enable read and write access to EEPROM */
381 #if defined(CONFIG_PCI)
384 * Memory space is mapped 1-1, but I/O space must start from 0.
387 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
388 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
389 #ifdef CONFIG_PHYS_64BIT
390 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
392 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
394 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
395 #ifdef CONFIG_PHYS_64BIT
396 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
398 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
401 /* controller 1, Slot 2, tgtid 1, Base address a000 */
402 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
403 #ifdef CONFIG_PHYS_64BIT
404 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
406 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
408 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
409 #ifdef CONFIG_PHYS_64BIT
410 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
412 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
415 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
416 #endif /* CONFIG_PCI */
418 #if defined(CONFIG_TSEC_ENET)
420 #define CONFIG_TSEC1_NAME "eTSEC1"
422 #define CONFIG_TSEC2_NAME "eTSEC2"
424 #define CONFIG_TSEC3_NAME "eTSEC3"
426 #define TSEC1_PHY_ADDR 2
427 #define TSEC2_PHY_ADDR 0
428 #define TSEC3_PHY_ADDR 1
430 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
431 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
432 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
434 #define TSEC1_PHYIDX 0
435 #define TSEC2_PHYIDX 0
436 #define TSEC3_PHYIDX 0
437 #endif /* CONFIG_TSEC_ENET */
442 #if defined(CONFIG_SDCARD)
443 #define CONFIG_FSL_FIXED_MMC_LOCATION
444 #elif defined(CONFIG_MTD_RAW_NAND)
445 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
446 #ifdef CONFIG_TPL_BUILD
447 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
449 #elif defined(CONFIG_SYS_RAMBOOT)
450 #define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
453 #define CONFIG_LOADS_ECHO /* echo on for serial download */
454 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
459 #define CONFIG_HAS_FSL_DR_USB
461 #if defined(CONFIG_HAS_FSL_DR_USB)
462 #ifdef CONFIG_USB_EHCI_HCD
463 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
467 #if defined(CONFIG_TARGET_P1020RDB_PD)
468 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
472 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
476 * Miscellaneous configurable options
480 * For booting Linux, the board info and command line data
481 * have to be in the first 64 MB of memory, since this is
482 * the maximum mapped by the Linux kernel during initialization.
484 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
485 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
488 * Environment Configuration
490 #define CONFIG_HOSTNAME "unknown"
491 #define CONFIG_ROOTPATH "/opt/nfsroot"
492 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
495 #define __NOR_RST_CMD \
496 norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NOR 1; \
497 i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
500 #define __SPI_RST_CMD \
501 spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SPI 1; \
502 i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
505 #define __SD_RST_CMD \
506 sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SD 1; \
507 i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
509 #ifdef __SW_BOOT_NAND
510 #define __NAND_RST_CMD \
511 nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NAND 1; \
512 i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
514 #ifdef __SW_BOOT_PCIE
515 #define __PCIE_RST_CMD \
516 pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_PCIE 1; \
517 i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
520 #define CONFIG_EXTRA_ENV_SETTINGS \
522 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
523 "loadaddr=1000000\0" \
524 "bootfile=uImage\0" \
525 "tftpflash=tftpboot $loadaddr $uboot; " \
526 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
527 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
528 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
529 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
530 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
531 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
532 "consoledev=ttyS0\0" \
533 "ramdiskaddr=2000000\0" \
534 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
535 "fdtaddr=1e00000\0" \
537 "jffs2nor=mtdblock3\0" \
538 "norbootaddr=ef080000\0" \
539 "norfdtaddr=ef040000\0" \
540 "jffs2nand=mtdblock9\0" \
541 "nandbootaddr=100000\0" \
542 "nandfdtaddr=80000\0" \
543 "ramdisk_size=120000\0" \
545 "map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_LO)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \
546 "map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_UP)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \
547 __stringify(__NOR_RST_CMD)"\0" \
548 __stringify(__SPI_RST_CMD)"\0" \
549 __stringify(__SD_RST_CMD)"\0" \
550 __stringify(__NAND_RST_CMD)"\0" \
551 __stringify(__PCIE_RST_CMD)"\0"
553 #define CONFIG_USB_FAT_BOOT \
554 "setenv bootargs root=/dev/ram rw " \
555 "console=$consoledev,$baudrate $othbootargs " \
556 "ramdisk_size=$ramdisk_size;" \
558 "fatload usb 0:2 $loadaddr $bootfile;" \
559 "fatload usb 0:2 $fdtaddr $fdtfile;" \
560 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
561 "bootm $loadaddr $ramdiskaddr $fdtaddr"
563 #define CONFIG_USB_EXT2_BOOT \
564 "setenv bootargs root=/dev/ram rw " \
565 "console=$consoledev,$baudrate $othbootargs " \
566 "ramdisk_size=$ramdisk_size;" \
568 "ext2load usb 0:4 $loadaddr $bootfile;" \
569 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
570 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
571 "bootm $loadaddr $ramdiskaddr $fdtaddr"
573 #define CONFIG_NORBOOT \
574 "setenv bootargs root=/dev/$jffs2nor rw " \
575 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
576 "bootm $norbootaddr - $norfdtaddr"
578 #endif /* __CONFIG_H */