1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * QorIQ RDB boards configuration file
13 #include <linux/stringify.h>
15 #if defined(CONFIG_TARGET_P1020RDB_PC)
16 #define CONFIG_BOARDNAME "P1020RDB-PC"
17 #define CONFIG_NAND_FSL_ELBC
18 #define CONFIG_VSC7385_ENET
20 #define __SW_BOOT_MASK 0x03
21 #define __SW_BOOT_NOR 0x5c
22 #define __SW_BOOT_SPI 0x1c
23 #define __SW_BOOT_SD 0x9c
24 #define __SW_BOOT_NAND 0xec
25 #define __SW_BOOT_PCIE 0x6c
26 #define CONFIG_SYS_L2_SIZE (256 << 10)
30 * P1020RDB-PD board has user selectable switches for evaluating different
31 * frequency and boot options for the P1020 device. The table that
32 * follow describe the available options. The front six binary number was in
33 * accordance with SW3[1:6].
34 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
35 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
36 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
37 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
38 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
39 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
40 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
42 #if defined(CONFIG_TARGET_P1020RDB_PD)
43 #define CONFIG_BOARDNAME "P1020RDB-PD"
44 #define CONFIG_NAND_FSL_ELBC
45 #define CONFIG_VSC7385_ENET
47 #define __SW_BOOT_MASK 0x03
48 #define __SW_BOOT_NOR 0x64
49 #define __SW_BOOT_SPI 0x34
50 #define __SW_BOOT_SD 0x24
51 #define __SW_BOOT_NAND 0x44
52 #define __SW_BOOT_PCIE 0x74
53 #define CONFIG_SYS_L2_SIZE (256 << 10)
55 * Dynamic MTD Partition support with mtdparts
59 #if defined(CONFIG_TARGET_P1021RDB)
60 #define CONFIG_BOARDNAME "P1021RDB-PC"
61 #define CONFIG_NAND_FSL_ELBC
62 #define CONFIG_VSC7385_ENET
63 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
64 addresses in the LBC */
65 #define __SW_BOOT_MASK 0x03
66 #define __SW_BOOT_NOR 0x5c
67 #define __SW_BOOT_SPI 0x1c
68 #define __SW_BOOT_SD 0x9c
69 #define __SW_BOOT_NAND 0xec
70 #define __SW_BOOT_PCIE 0x6c
71 #define CONFIG_SYS_L2_SIZE (256 << 10)
73 * Dynamic MTD Partition support with mtdparts
77 #if defined(CONFIG_TARGET_P1024RDB)
78 #define CONFIG_BOARDNAME "P1024RDB"
79 #define CONFIG_NAND_FSL_ELBC
81 #define __SW_BOOT_MASK 0xf3
82 #define __SW_BOOT_NOR 0x00
83 #define __SW_BOOT_SPI 0x08
84 #define __SW_BOOT_SD 0x04
85 #define __SW_BOOT_NAND 0x0c
86 #define CONFIG_SYS_L2_SIZE (256 << 10)
89 #if defined(CONFIG_TARGET_P2020RDB)
90 #define CONFIG_BOARDNAME "P2020RDB-PC"
91 #define CONFIG_NAND_FSL_ELBC
92 #define CONFIG_VSC7385_ENET
93 #define __SW_BOOT_MASK 0x03
94 #define __SW_BOOT_NOR 0xc8
95 #define __SW_BOOT_SPI 0x28
96 #define __SW_BOOT_SD 0x68 /* or 0x18 */
97 #define __SW_BOOT_NAND 0xe8
98 #define __SW_BOOT_PCIE 0xa8
99 #define CONFIG_SYS_L2_SIZE (512 << 10)
101 * Dynamic MTD Partition support with mtdparts
106 #define CONFIG_SPL_FLUSH_IMAGE
107 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
108 #define CONFIG_SPL_PAD_TO 0x20000
109 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
110 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
111 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
112 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
113 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
114 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
115 #ifdef CONFIG_SPL_BUILD
116 #define CONFIG_SPL_COMMON_INIT_DDR
120 #ifdef CONFIG_SPIFLASH
121 #define CONFIG_SPL_SPI_FLASH_MINIMAL
122 #define CONFIG_SPL_FLUSH_IMAGE
123 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
124 #define CONFIG_SPL_PAD_TO 0x20000
125 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
126 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
127 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
128 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
129 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
130 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
131 #ifdef CONFIG_SPL_BUILD
132 #define CONFIG_SPL_COMMON_INIT_DDR
136 #ifdef CONFIG_MTD_RAW_NAND
137 #ifdef CONFIG_TPL_BUILD
138 #define CONFIG_SPL_FLUSH_IMAGE
139 #define CONFIG_SPL_NAND_INIT
140 #define CONFIG_SPL_COMMON_INIT_DDR
141 #define CONFIG_SPL_MAX_SIZE (128 << 10)
142 #define CONFIG_TPL_TEXT_BASE 0xf8f81000
143 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
144 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
145 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
146 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
147 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
148 #elif defined(CONFIG_SPL_BUILD)
149 #define CONFIG_SPL_INIT_MINIMAL
150 #define CONFIG_SPL_FLUSH_IMAGE
151 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
152 #define CONFIG_SPL_MAX_SIZE 4096
153 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
154 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
155 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
156 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
157 #endif /* not CONFIG_TPL_BUILD */
159 #define CONFIG_SPL_PAD_TO 0x20000
160 #define CONFIG_TPL_PAD_TO 0x20000
161 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
164 #ifndef CONFIG_RESET_VECTOR_ADDRESS
165 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
168 #ifndef CONFIG_SYS_MONITOR_BASE
169 #ifdef CONFIG_TPL_BUILD
170 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
171 #elif defined(CONFIG_SPL_BUILD)
172 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
174 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
178 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
179 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
180 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
182 #define CONFIG_SYS_SATA_MAX_DEVICE 2
185 #if defined(CONFIG_TARGET_P2020RDB)
186 #define CONFIG_SYS_CLK_FREQ 100000000
188 #define CONFIG_SYS_CLK_FREQ 66666666
190 #define CONFIG_DDR_CLK_FREQ 66666666
192 #define CONFIG_HWCONFIG
194 * These can be toggled for performance analysis, otherwise use default.
196 #define CONFIG_L2_CACHE
199 #define CONFIG_ENABLE_36BIT_PHYS
201 #define CONFIG_SYS_CCSRBAR 0xffe00000
202 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
204 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
206 #ifdef CONFIG_SPL_BUILD
207 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
211 #define CONFIG_SYS_DDR_RAW_TIMING
212 #define CONFIG_DDR_SPD
213 #define CONFIG_SYS_SPD_BUS_NUM 1
214 #define SPD_EEPROM_ADDRESS 0x52
216 #if defined(CONFIG_TARGET_P1020RDB_PD)
217 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
218 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
220 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
221 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
223 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
224 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
225 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
227 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
229 /* Default settings for DDR3 */
230 #ifndef CONFIG_TARGET_P2020RDB
231 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
232 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
233 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
234 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
235 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
236 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
238 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
239 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
240 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
241 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
243 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
244 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
245 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
246 #define CONFIG_SYS_DDR_RCW_1 0x00000000
247 #define CONFIG_SYS_DDR_RCW_2 0x00000000
248 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
249 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
250 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
251 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
253 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
254 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
255 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
256 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
257 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
258 #define CONFIG_SYS_DDR_MODE_1 0x40461520
259 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
260 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
266 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
267 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
268 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
269 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
271 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
272 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
273 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
274 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
275 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
276 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
277 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
281 * Local Bus Definitions
283 #if defined(CONFIG_TARGET_P1020RDB_PD)
284 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
285 #define CONFIG_SYS_FLASH_BASE 0xec000000
287 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
288 #define CONFIG_SYS_FLASH_BASE 0xef000000
291 #ifdef CONFIG_PHYS_64BIT
292 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
294 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
297 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
300 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
302 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
303 #define CONFIG_SYS_FLASH_QUIET_TEST
304 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
306 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
308 #undef CONFIG_SYS_FLASH_CHECKSUM
309 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
310 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
312 #define CONFIG_SYS_FLASH_EMPTY_INFO
315 #ifdef CONFIG_NAND_FSL_ELBC
316 #define CONFIG_SYS_NAND_BASE 0xff800000
317 #ifdef CONFIG_PHYS_64BIT
318 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
320 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
323 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
324 #define CONFIG_SYS_MAX_NAND_DEVICE 1
325 #if defined(CONFIG_TARGET_P1020RDB_PD)
326 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
328 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
331 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
332 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
333 | BR_PS_8 /* Port Size = 8 bit */ \
334 | BR_MS_FCM /* MSEL = FCM */ \
336 #if defined(CONFIG_TARGET_P1020RDB_PD)
337 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
338 | OR_FCM_PGS /* Large Page*/ \
346 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
354 #endif /* CONFIG_NAND_FSL_ELBC */
356 #define CONFIG_SYS_INIT_RAM_LOCK
357 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
358 #ifdef CONFIG_PHYS_64BIT
359 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
360 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
361 /* The assembler doesn't like typecast */
362 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
363 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
364 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
366 /* Initial L1 address */
367 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
368 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
369 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
371 /* Size of used area in RAM */
372 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
374 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
375 GENERATED_GBL_DATA_SIZE)
376 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
378 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
379 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
381 #define CONFIG_SYS_CPLD_BASE 0xffa00000
382 #ifdef CONFIG_PHYS_64BIT
383 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
385 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
387 /* CPLD config size: 1Mb */
388 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
390 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
392 #define CONFIG_SYS_PMC_BASE 0xff980000
393 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
394 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
396 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
397 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
400 #ifdef CONFIG_MTD_RAW_NAND
401 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
402 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
403 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
404 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
406 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
407 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
408 #ifdef CONFIG_NAND_FSL_ELBC
409 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
410 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
413 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
414 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
417 #ifdef CONFIG_VSC7385_ENET
418 #define __VSCFW_ADDR "vscfw_addr=ef000000"
419 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
421 #ifdef CONFIG_PHYS_64BIT
422 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
424 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
427 #define CONFIG_SYS_VSC7385_BR_PRELIM \
428 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
429 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
430 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
431 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
433 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
434 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
436 /* The size of the VSC7385 firmware image */
437 #define CONFIG_VSC7385_IMAGE_SIZE 8192
441 * Config the L2 Cache as L2 SRAM
443 #if defined(CONFIG_SPL_BUILD)
444 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
445 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
446 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
447 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
448 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
449 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
450 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
451 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
452 #if defined(CONFIG_TARGET_P2020RDB)
453 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
455 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
457 #elif defined(CONFIG_MTD_RAW_NAND)
458 #ifdef CONFIG_TPL_BUILD
459 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
460 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
461 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
462 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
463 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
464 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
465 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
466 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
468 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
469 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
470 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
471 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
472 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
473 #endif /* CONFIG_TPL_BUILD */
477 /* Serial Port - controlled on board with jumper J8
481 #undef CONFIG_SERIAL_SOFTWARE_FIFO
482 #define CONFIG_SYS_NS16550_SERIAL
483 #define CONFIG_SYS_NS16550_REG_SIZE 1
484 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
485 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
486 #define CONFIG_NS16550_MIN_FUNCTIONS
489 #define CONFIG_SYS_BAUDRATE_TABLE \
490 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
492 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
493 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
496 #ifndef CONFIG_DM_I2C
497 #define CONFIG_SYS_I2C
498 #define CONFIG_SYS_FSL_I2C_SPEED 400000
499 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
500 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
501 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
502 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
503 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
504 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
506 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
507 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
510 #define CONFIG_SYS_I2C_FSL
511 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
512 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
517 #undef CONFIG_ID_EEPROM
519 #define CONFIG_RTC_PT7C4338
520 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
521 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
523 /* enable read and write access to EEPROM */
524 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
525 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
526 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
528 #if defined(CONFIG_PCI)
531 * Memory space is mapped 1-1, but I/O space must start from 0.
534 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
535 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
536 #ifdef CONFIG_PHYS_64BIT
537 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
539 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
541 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
542 #ifdef CONFIG_PHYS_64BIT
543 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
545 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
548 /* controller 1, Slot 2, tgtid 1, Base address a000 */
549 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
550 #ifdef CONFIG_PHYS_64BIT
551 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
553 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
555 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
556 #ifdef CONFIG_PHYS_64BIT
557 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
559 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
562 #if !defined(CONFIG_DM_PCI)
563 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
564 #define CONFIG_PCI_INDIRECT_BRIDGE
565 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
566 #ifdef CONFIG_PHYS_64BIT
567 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
569 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
571 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
572 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
573 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
575 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
576 #ifdef CONFIG_PHYS_64BIT
577 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
579 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
581 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
582 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
583 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
586 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
587 #endif /* CONFIG_PCI */
589 #if defined(CONFIG_TSEC_ENET)
591 #define CONFIG_TSEC1_NAME "eTSEC1"
593 #define CONFIG_TSEC2_NAME "eTSEC2"
595 #define CONFIG_TSEC3_NAME "eTSEC3"
597 #define TSEC1_PHY_ADDR 2
598 #define TSEC2_PHY_ADDR 0
599 #define TSEC3_PHY_ADDR 1
601 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
602 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
603 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
605 #define TSEC1_PHYIDX 0
606 #define TSEC2_PHYIDX 0
607 #define TSEC3_PHYIDX 0
609 #define CONFIG_ETHPRIME "eTSEC1"
611 #define CONFIG_HAS_ETH0
612 #define CONFIG_HAS_ETH1
613 #define CONFIG_HAS_ETH2
614 #endif /* CONFIG_TSEC_ENET */
617 /* QE microcode/firmware address */
618 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
619 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
620 #endif /* CONFIG_QE */
625 #if defined(CONFIG_SDCARD)
626 #define CONFIG_FSL_FIXED_MMC_LOCATION
627 #elif defined(CONFIG_MTD_RAW_NAND)
628 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
629 #ifdef CONFIG_TPL_BUILD
630 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
632 #elif defined(CONFIG_SYS_RAMBOOT)
633 #define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
636 #define CONFIG_LOADS_ECHO /* echo on for serial download */
637 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
642 #define CONFIG_HAS_FSL_DR_USB
644 #if defined(CONFIG_HAS_FSL_DR_USB)
645 #ifdef CONFIG_USB_EHCI_HCD
646 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
647 #define CONFIG_USB_EHCI_FSL
651 #if defined(CONFIG_TARGET_P1020RDB_PD)
652 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
656 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
659 #undef CONFIG_WATCHDOG /* watchdog disabled */
662 * Miscellaneous configurable options
664 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
667 * For booting Linux, the board info and command line data
668 * have to be in the first 64 MB of memory, since this is
669 * the maximum mapped by the Linux kernel during initialization.
671 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
672 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
674 #if defined(CONFIG_CMD_KGDB)
675 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
679 * Environment Configuration
681 #define CONFIG_HOSTNAME "unknown"
682 #define CONFIG_ROOTPATH "/opt/nfsroot"
683 #define CONFIG_BOOTFILE "uImage"
684 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
686 /* default location for tftp and bootm */
687 #define CONFIG_LOADADDR 1000000
690 #define __NOR_RST_CMD \
691 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
692 i2c mw 18 3 __SW_BOOT_MASK 1; reset
695 #define __SPI_RST_CMD \
696 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
697 i2c mw 18 3 __SW_BOOT_MASK 1; reset
700 #define __SD_RST_CMD \
701 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
702 i2c mw 18 3 __SW_BOOT_MASK 1; reset
704 #ifdef __SW_BOOT_NAND
705 #define __NAND_RST_CMD \
706 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
707 i2c mw 18 3 __SW_BOOT_MASK 1; reset
709 #ifdef __SW_BOOT_PCIE
710 #define __PCIE_RST_CMD \
711 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
712 i2c mw 18 3 __SW_BOOT_MASK 1; reset
715 #define CONFIG_EXTRA_ENV_SETTINGS \
717 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
718 "loadaddr=1000000\0" \
719 "bootfile=uImage\0" \
720 "tftpflash=tftpboot $loadaddr $uboot; " \
721 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
722 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
723 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
724 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
725 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
726 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
727 "consoledev=ttyS0\0" \
728 "ramdiskaddr=2000000\0" \
729 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
730 "fdtaddr=1e00000\0" \
732 "jffs2nor=mtdblock3\0" \
733 "norbootaddr=ef080000\0" \
734 "norfdtaddr=ef040000\0" \
735 "jffs2nand=mtdblock9\0" \
736 "nandbootaddr=100000\0" \
737 "nandfdtaddr=80000\0" \
738 "ramdisk_size=120000\0" \
739 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
740 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
741 __stringify(__VSCFW_ADDR)"\0" \
742 __stringify(__NOR_RST_CMD)"\0" \
743 __stringify(__SPI_RST_CMD)"\0" \
744 __stringify(__SD_RST_CMD)"\0" \
745 __stringify(__NAND_RST_CMD)"\0" \
746 __stringify(__PCIE_RST_CMD)"\0"
748 #define CONFIG_NFSBOOTCOMMAND \
749 "setenv bootargs root=/dev/nfs rw " \
750 "nfsroot=$serverip:$rootpath " \
751 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
752 "console=$consoledev,$baudrate $othbootargs;" \
753 "tftp $loadaddr $bootfile;" \
754 "tftp $fdtaddr $fdtfile;" \
755 "bootm $loadaddr - $fdtaddr"
757 #define CONFIG_HDBOOT \
758 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
759 "console=$consoledev,$baudrate $othbootargs;" \
761 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
762 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
763 "bootm $loadaddr - $fdtaddr"
765 #define CONFIG_USB_FAT_BOOT \
766 "setenv bootargs root=/dev/ram rw " \
767 "console=$consoledev,$baudrate $othbootargs " \
768 "ramdisk_size=$ramdisk_size;" \
770 "fatload usb 0:2 $loadaddr $bootfile;" \
771 "fatload usb 0:2 $fdtaddr $fdtfile;" \
772 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
773 "bootm $loadaddr $ramdiskaddr $fdtaddr"
775 #define CONFIG_USB_EXT2_BOOT \
776 "setenv bootargs root=/dev/ram rw " \
777 "console=$consoledev,$baudrate $othbootargs " \
778 "ramdisk_size=$ramdisk_size;" \
780 "ext2load usb 0:4 $loadaddr $bootfile;" \
781 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
782 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
783 "bootm $loadaddr $ramdiskaddr $fdtaddr"
785 #define CONFIG_NORBOOT \
786 "setenv bootargs root=/dev/$jffs2nor rw " \
787 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
788 "bootm $norbootaddr - $norfdtaddr"
790 #define CONFIG_RAMBOOTCOMMAND \
791 "setenv bootargs root=/dev/ram rw " \
792 "console=$consoledev,$baudrate $othbootargs " \
793 "ramdisk_size=$ramdisk_size;" \
794 "tftp $ramdiskaddr $ramdiskfile;" \
795 "tftp $loadaddr $bootfile;" \
796 "tftp $fdtaddr $fdtfile;" \
797 "bootm $loadaddr $ramdiskaddr $fdtaddr"
799 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
801 #endif /* __CONFIG_H */