1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * QorIQ RDB boards configuration file
13 #include <linux/stringify.h>
15 #if defined(CONFIG_TARGET_P1020MBG)
16 #define CONFIG_BOARDNAME "P1020MBG-PC"
17 #define CONFIG_VSC7385_ENET
19 #define __SW_BOOT_MASK 0x03
20 #define __SW_BOOT_NOR 0xe4
21 #define __SW_BOOT_SD 0x54
22 #define CONFIG_SYS_L2_SIZE (256 << 10)
25 #if defined(CONFIG_TARGET_P1020UTM)
26 #define CONFIG_BOARDNAME "P1020UTM-PC"
27 #define __SW_BOOT_MASK 0x03
28 #define __SW_BOOT_NOR 0xe0
29 #define __SW_BOOT_SD 0x50
30 #define CONFIG_SYS_L2_SIZE (256 << 10)
33 #if defined(CONFIG_TARGET_P1020RDB_PC)
34 #define CONFIG_BOARDNAME "P1020RDB-PC"
35 #define CONFIG_NAND_FSL_ELBC
36 #define CONFIG_VSC7385_ENET
38 #define __SW_BOOT_MASK 0x03
39 #define __SW_BOOT_NOR 0x5c
40 #define __SW_BOOT_SPI 0x1c
41 #define __SW_BOOT_SD 0x9c
42 #define __SW_BOOT_NAND 0xec
43 #define __SW_BOOT_PCIE 0x6c
44 #define CONFIG_SYS_L2_SIZE (256 << 10)
48 * P1020RDB-PD board has user selectable switches for evaluating different
49 * frequency and boot options for the P1020 device. The table that
50 * follow describe the available options. The front six binary number was in
51 * accordance with SW3[1:6].
52 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
53 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
54 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
55 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
56 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
57 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
58 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
60 #if defined(CONFIG_TARGET_P1020RDB_PD)
61 #define CONFIG_BOARDNAME "P1020RDB-PD"
62 #define CONFIG_NAND_FSL_ELBC
63 #define CONFIG_VSC7385_ENET
65 #define __SW_BOOT_MASK 0x03
66 #define __SW_BOOT_NOR 0x64
67 #define __SW_BOOT_SPI 0x34
68 #define __SW_BOOT_SD 0x24
69 #define __SW_BOOT_NAND 0x44
70 #define __SW_BOOT_PCIE 0x74
71 #define CONFIG_SYS_L2_SIZE (256 << 10)
73 * Dynamic MTD Partition support with mtdparts
77 #if defined(CONFIG_TARGET_P1021RDB)
78 #define CONFIG_BOARDNAME "P1021RDB-PC"
79 #define CONFIG_NAND_FSL_ELBC
80 #define CONFIG_VSC7385_ENET
81 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
82 addresses in the LBC */
83 #define __SW_BOOT_MASK 0x03
84 #define __SW_BOOT_NOR 0x5c
85 #define __SW_BOOT_SPI 0x1c
86 #define __SW_BOOT_SD 0x9c
87 #define __SW_BOOT_NAND 0xec
88 #define __SW_BOOT_PCIE 0x6c
89 #define CONFIG_SYS_L2_SIZE (256 << 10)
91 * Dynamic MTD Partition support with mtdparts
95 #if defined(CONFIG_TARGET_P1024RDB)
96 #define CONFIG_BOARDNAME "P1024RDB"
97 #define CONFIG_NAND_FSL_ELBC
99 #define __SW_BOOT_MASK 0xf3
100 #define __SW_BOOT_NOR 0x00
101 #define __SW_BOOT_SPI 0x08
102 #define __SW_BOOT_SD 0x04
103 #define __SW_BOOT_NAND 0x0c
104 #define CONFIG_SYS_L2_SIZE (256 << 10)
107 #if defined(CONFIG_TARGET_P2020RDB)
108 #define CONFIG_BOARDNAME "P2020RDB-PC"
109 #define CONFIG_NAND_FSL_ELBC
110 #define CONFIG_VSC7385_ENET
111 #define __SW_BOOT_MASK 0x03
112 #define __SW_BOOT_NOR 0xc8
113 #define __SW_BOOT_SPI 0x28
114 #define __SW_BOOT_SD 0x68 /* or 0x18 */
115 #define __SW_BOOT_NAND 0xe8
116 #define __SW_BOOT_PCIE 0xa8
117 #define CONFIG_SYS_L2_SIZE (512 << 10)
119 * Dynamic MTD Partition support with mtdparts
124 #define CONFIG_SPL_FLUSH_IMAGE
125 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
126 #define CONFIG_SPL_PAD_TO 0x20000
127 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
128 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
129 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
130 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
131 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
132 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
133 #ifdef CONFIG_SPL_BUILD
134 #define CONFIG_SPL_COMMON_INIT_DDR
138 #ifdef CONFIG_SPIFLASH
139 #define CONFIG_SPL_SPI_FLASH_MINIMAL
140 #define CONFIG_SPL_FLUSH_IMAGE
141 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
142 #define CONFIG_SPL_PAD_TO 0x20000
143 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
144 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
145 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
146 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
147 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
148 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
149 #ifdef CONFIG_SPL_BUILD
150 #define CONFIG_SPL_COMMON_INIT_DDR
154 #ifdef CONFIG_MTD_RAW_NAND
155 #ifdef CONFIG_TPL_BUILD
156 #define CONFIG_SPL_FLUSH_IMAGE
157 #define CONFIG_SPL_NAND_INIT
158 #define CONFIG_SPL_COMMON_INIT_DDR
159 #define CONFIG_SPL_MAX_SIZE (128 << 10)
160 #define CONFIG_TPL_TEXT_BASE 0xf8f81000
161 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
162 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
163 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
164 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
165 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
166 #elif defined(CONFIG_SPL_BUILD)
167 #define CONFIG_SPL_INIT_MINIMAL
168 #define CONFIG_SPL_FLUSH_IMAGE
169 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
170 #define CONFIG_SPL_MAX_SIZE 4096
171 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
172 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
173 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
174 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
175 #endif /* not CONFIG_TPL_BUILD */
177 #define CONFIG_SPL_PAD_TO 0x20000
178 #define CONFIG_TPL_PAD_TO 0x20000
179 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
182 #ifndef CONFIG_RESET_VECTOR_ADDRESS
183 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
186 #ifndef CONFIG_SYS_MONITOR_BASE
187 #ifdef CONFIG_TPL_BUILD
188 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
189 #elif defined(CONFIG_SPL_BUILD)
190 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
192 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
196 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
197 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
198 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
200 #define CONFIG_SYS_SATA_MAX_DEVICE 2
203 #if defined(CONFIG_TARGET_P2020RDB)
204 #define CONFIG_SYS_CLK_FREQ 100000000
206 #define CONFIG_SYS_CLK_FREQ 66666666
208 #define CONFIG_DDR_CLK_FREQ 66666666
210 #define CONFIG_HWCONFIG
212 * These can be toggled for performance analysis, otherwise use default.
214 #define CONFIG_L2_CACHE
217 #define CONFIG_ENABLE_36BIT_PHYS
219 #define CONFIG_SYS_CCSRBAR 0xffe00000
220 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
222 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
224 #ifdef CONFIG_SPL_BUILD
225 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
229 #define CONFIG_SYS_DDR_RAW_TIMING
230 #define CONFIG_DDR_SPD
231 #define CONFIG_SYS_SPD_BUS_NUM 1
232 #define SPD_EEPROM_ADDRESS 0x52
234 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
235 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
236 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
238 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
239 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
241 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
242 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
243 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
245 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
247 /* Default settings for DDR3 */
248 #ifndef CONFIG_TARGET_P2020RDB
249 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
250 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
251 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
252 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
253 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
254 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
256 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
257 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
258 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
259 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
261 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
262 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
263 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
264 #define CONFIG_SYS_DDR_RCW_1 0x00000000
265 #define CONFIG_SYS_DDR_RCW_2 0x00000000
266 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
267 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
268 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
269 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
271 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
272 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
273 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
274 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
275 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
276 #define CONFIG_SYS_DDR_MODE_1 0x40461520
277 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
278 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
284 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
285 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
286 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
287 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
289 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
290 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
291 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
292 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
293 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
294 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
295 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
299 * Local Bus Definitions
301 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
302 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
303 #define CONFIG_SYS_FLASH_BASE 0xec000000
304 #elif defined(CONFIG_TARGET_P1020UTM)
305 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
306 #define CONFIG_SYS_FLASH_BASE 0xee000000
308 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
309 #define CONFIG_SYS_FLASH_BASE 0xef000000
312 #ifdef CONFIG_PHYS_64BIT
313 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
315 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
318 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
321 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
323 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
324 #define CONFIG_SYS_FLASH_QUIET_TEST
325 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
327 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
329 #undef CONFIG_SYS_FLASH_CHECKSUM
330 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
331 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
333 #define CONFIG_SYS_FLASH_EMPTY_INFO
336 #ifdef CONFIG_NAND_FSL_ELBC
337 #define CONFIG_SYS_NAND_BASE 0xff800000
338 #ifdef CONFIG_PHYS_64BIT
339 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
341 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
344 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
345 #define CONFIG_SYS_MAX_NAND_DEVICE 1
346 #if defined(CONFIG_TARGET_P1020RDB_PD)
347 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
349 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
352 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
353 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
354 | BR_PS_8 /* Port Size = 8 bit */ \
355 | BR_MS_FCM /* MSEL = FCM */ \
357 #if defined(CONFIG_TARGET_P1020RDB_PD)
358 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
359 | OR_FCM_PGS /* Large Page*/ \
367 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
375 #endif /* CONFIG_NAND_FSL_ELBC */
377 #define CONFIG_SYS_INIT_RAM_LOCK
378 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
379 #ifdef CONFIG_PHYS_64BIT
380 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
381 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
382 /* The assembler doesn't like typecast */
383 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
384 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
385 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
387 /* Initial L1 address */
388 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
389 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
390 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
392 /* Size of used area in RAM */
393 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
395 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
396 GENERATED_GBL_DATA_SIZE)
397 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
399 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
400 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
402 #define CONFIG_SYS_CPLD_BASE 0xffa00000
403 #ifdef CONFIG_PHYS_64BIT
404 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
406 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
408 /* CPLD config size: 1Mb */
409 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
411 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
413 #define CONFIG_SYS_PMC_BASE 0xff980000
414 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
415 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
417 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
418 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
421 #ifdef CONFIG_MTD_RAW_NAND
422 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
423 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
424 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
425 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
427 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
428 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
429 #ifdef CONFIG_NAND_FSL_ELBC
430 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
431 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
434 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
435 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
438 #ifdef CONFIG_VSC7385_ENET
439 #define __VSCFW_ADDR "vscfw_addr=ef000000"
440 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
442 #ifdef CONFIG_PHYS_64BIT
443 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
445 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
448 #define CONFIG_SYS_VSC7385_BR_PRELIM \
449 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
450 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
451 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
452 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
454 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
455 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
457 /* The size of the VSC7385 firmware image */
458 #define CONFIG_VSC7385_IMAGE_SIZE 8192
462 * Config the L2 Cache as L2 SRAM
464 #if defined(CONFIG_SPL_BUILD)
465 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
466 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
467 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
468 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
469 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
470 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
471 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
472 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
473 #if defined(CONFIG_TARGET_P2020RDB)
474 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
476 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
478 #elif defined(CONFIG_MTD_RAW_NAND)
479 #ifdef CONFIG_TPL_BUILD
480 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
481 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
482 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
483 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
484 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
485 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
486 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
487 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
489 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
490 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
491 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
492 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
493 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
494 #endif /* CONFIG_TPL_BUILD */
498 /* Serial Port - controlled on board with jumper J8
502 #undef CONFIG_SERIAL_SOFTWARE_FIFO
503 #define CONFIG_SYS_NS16550_SERIAL
504 #define CONFIG_SYS_NS16550_REG_SIZE 1
505 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
506 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
507 #define CONFIG_NS16550_MIN_FUNCTIONS
510 #define CONFIG_SYS_BAUDRATE_TABLE \
511 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
513 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
514 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
517 #ifndef CONFIG_DM_I2C
518 #define CONFIG_SYS_I2C
519 #define CONFIG_SYS_FSL_I2C_SPEED 400000
520 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
521 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
522 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
523 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
524 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
525 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
527 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
528 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
531 #define CONFIG_SYS_I2C_FSL
532 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
533 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
538 #undef CONFIG_ID_EEPROM
540 #define CONFIG_RTC_PT7C4338
541 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
542 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
544 /* enable read and write access to EEPROM */
545 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
546 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
547 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
549 #if defined(CONFIG_PCI)
552 * Memory space is mapped 1-1, but I/O space must start from 0.
555 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
556 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
557 #ifdef CONFIG_PHYS_64BIT
558 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
560 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
562 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
563 #ifdef CONFIG_PHYS_64BIT
564 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
566 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
569 /* controller 1, Slot 2, tgtid 1, Base address a000 */
570 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
571 #ifdef CONFIG_PHYS_64BIT
572 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
574 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
576 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
577 #ifdef CONFIG_PHYS_64BIT
578 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
580 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
583 #if !defined(CONFIG_DM_PCI)
584 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
585 #define CONFIG_PCI_INDIRECT_BRIDGE
586 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
587 #ifdef CONFIG_PHYS_64BIT
588 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
590 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
592 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
593 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
594 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
596 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
597 #ifdef CONFIG_PHYS_64BIT
598 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
600 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
602 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
603 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
604 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
607 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
608 #endif /* CONFIG_PCI */
610 #if defined(CONFIG_TSEC_ENET)
612 #define CONFIG_TSEC1_NAME "eTSEC1"
614 #define CONFIG_TSEC2_NAME "eTSEC2"
616 #define CONFIG_TSEC3_NAME "eTSEC3"
618 #define TSEC1_PHY_ADDR 2
619 #define TSEC2_PHY_ADDR 0
620 #define TSEC3_PHY_ADDR 1
622 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
623 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
624 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
626 #define TSEC1_PHYIDX 0
627 #define TSEC2_PHYIDX 0
628 #define TSEC3_PHYIDX 0
630 #define CONFIG_ETHPRIME "eTSEC1"
632 #define CONFIG_HAS_ETH0
633 #define CONFIG_HAS_ETH1
634 #define CONFIG_HAS_ETH2
635 #endif /* CONFIG_TSEC_ENET */
638 /* QE microcode/firmware address */
639 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
640 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
641 #endif /* CONFIG_QE */
646 #if defined(CONFIG_SDCARD)
647 #define CONFIG_FSL_FIXED_MMC_LOCATION
648 #elif defined(CONFIG_MTD_RAW_NAND)
649 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
650 #ifdef CONFIG_TPL_BUILD
651 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
653 #elif defined(CONFIG_SYS_RAMBOOT)
654 #define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
657 #define CONFIG_LOADS_ECHO /* echo on for serial download */
658 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
663 #define CONFIG_HAS_FSL_DR_USB
665 #if defined(CONFIG_HAS_FSL_DR_USB)
666 #ifdef CONFIG_USB_EHCI_HCD
667 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
668 #define CONFIG_USB_EHCI_FSL
672 #if defined(CONFIG_TARGET_P1020RDB_PD)
673 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
677 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
680 #undef CONFIG_WATCHDOG /* watchdog disabled */
683 * Miscellaneous configurable options
685 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
688 * For booting Linux, the board info and command line data
689 * have to be in the first 64 MB of memory, since this is
690 * the maximum mapped by the Linux kernel during initialization.
692 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
693 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
695 #if defined(CONFIG_CMD_KGDB)
696 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
700 * Environment Configuration
702 #define CONFIG_HOSTNAME "unknown"
703 #define CONFIG_ROOTPATH "/opt/nfsroot"
704 #define CONFIG_BOOTFILE "uImage"
705 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
707 /* default location for tftp and bootm */
708 #define CONFIG_LOADADDR 1000000
711 #define __NOR_RST_CMD \
712 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
713 i2c mw 18 3 __SW_BOOT_MASK 1; reset
716 #define __SPI_RST_CMD \
717 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
718 i2c mw 18 3 __SW_BOOT_MASK 1; reset
721 #define __SD_RST_CMD \
722 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
723 i2c mw 18 3 __SW_BOOT_MASK 1; reset
725 #ifdef __SW_BOOT_NAND
726 #define __NAND_RST_CMD \
727 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
728 i2c mw 18 3 __SW_BOOT_MASK 1; reset
730 #ifdef __SW_BOOT_PCIE
731 #define __PCIE_RST_CMD \
732 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
733 i2c mw 18 3 __SW_BOOT_MASK 1; reset
736 #define CONFIG_EXTRA_ENV_SETTINGS \
738 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
739 "loadaddr=1000000\0" \
740 "bootfile=uImage\0" \
741 "tftpflash=tftpboot $loadaddr $uboot; " \
742 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
743 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
744 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
745 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
746 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
747 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
748 "consoledev=ttyS0\0" \
749 "ramdiskaddr=2000000\0" \
750 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
751 "fdtaddr=1e00000\0" \
753 "jffs2nor=mtdblock3\0" \
754 "norbootaddr=ef080000\0" \
755 "norfdtaddr=ef040000\0" \
756 "jffs2nand=mtdblock9\0" \
757 "nandbootaddr=100000\0" \
758 "nandfdtaddr=80000\0" \
759 "ramdisk_size=120000\0" \
760 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
761 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
762 __stringify(__VSCFW_ADDR)"\0" \
763 __stringify(__NOR_RST_CMD)"\0" \
764 __stringify(__SPI_RST_CMD)"\0" \
765 __stringify(__SD_RST_CMD)"\0" \
766 __stringify(__NAND_RST_CMD)"\0" \
767 __stringify(__PCIE_RST_CMD)"\0"
769 #define CONFIG_NFSBOOTCOMMAND \
770 "setenv bootargs root=/dev/nfs rw " \
771 "nfsroot=$serverip:$rootpath " \
772 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
773 "console=$consoledev,$baudrate $othbootargs;" \
774 "tftp $loadaddr $bootfile;" \
775 "tftp $fdtaddr $fdtfile;" \
776 "bootm $loadaddr - $fdtaddr"
778 #define CONFIG_HDBOOT \
779 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
780 "console=$consoledev,$baudrate $othbootargs;" \
782 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
783 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
784 "bootm $loadaddr - $fdtaddr"
786 #define CONFIG_USB_FAT_BOOT \
787 "setenv bootargs root=/dev/ram rw " \
788 "console=$consoledev,$baudrate $othbootargs " \
789 "ramdisk_size=$ramdisk_size;" \
791 "fatload usb 0:2 $loadaddr $bootfile;" \
792 "fatload usb 0:2 $fdtaddr $fdtfile;" \
793 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
794 "bootm $loadaddr $ramdiskaddr $fdtaddr"
796 #define CONFIG_USB_EXT2_BOOT \
797 "setenv bootargs root=/dev/ram rw " \
798 "console=$consoledev,$baudrate $othbootargs " \
799 "ramdisk_size=$ramdisk_size;" \
801 "ext2load usb 0:4 $loadaddr $bootfile;" \
802 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
803 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
804 "bootm $loadaddr $ramdiskaddr $fdtaddr"
806 #define CONFIG_NORBOOT \
807 "setenv bootargs root=/dev/$jffs2nor rw " \
808 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
809 "bootm $norbootaddr - $norfdtaddr"
811 #define CONFIG_RAMBOOTCOMMAND \
812 "setenv bootargs root=/dev/ram rw " \
813 "console=$consoledev,$baudrate $othbootargs " \
814 "ramdisk_size=$ramdisk_size;" \
815 "tftp $ramdiskaddr $ramdiskfile;" \
816 "tftp $loadaddr $bootfile;" \
817 "tftp $fdtaddr $fdtfile;" \
818 "bootm $loadaddr $ramdiskaddr $fdtaddr"
820 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
822 #endif /* __CONFIG_H */