1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
7 * QorIQ RDB boards configuration file
12 #if defined(CONFIG_TARGET_P1020MBG)
13 #define CONFIG_BOARDNAME "P1020MBG-PC"
14 #define CONFIG_VSC7385_ENET
16 #define __SW_BOOT_MASK 0x03
17 #define __SW_BOOT_NOR 0xe4
18 #define __SW_BOOT_SD 0x54
19 #define CONFIG_SYS_L2_SIZE (256 << 10)
22 #if defined(CONFIG_TARGET_P1020UTM)
23 #define CONFIG_BOARDNAME "P1020UTM-PC"
24 #define __SW_BOOT_MASK 0x03
25 #define __SW_BOOT_NOR 0xe0
26 #define __SW_BOOT_SD 0x50
27 #define CONFIG_SYS_L2_SIZE (256 << 10)
30 #if defined(CONFIG_TARGET_P1020RDB_PC)
31 #define CONFIG_BOARDNAME "P1020RDB-PC"
32 #define CONFIG_NAND_FSL_ELBC
33 #define CONFIG_VSC7385_ENET
35 #define __SW_BOOT_MASK 0x03
36 #define __SW_BOOT_NOR 0x5c
37 #define __SW_BOOT_SPI 0x1c
38 #define __SW_BOOT_SD 0x9c
39 #define __SW_BOOT_NAND 0xec
40 #define __SW_BOOT_PCIE 0x6c
41 #define CONFIG_SYS_L2_SIZE (256 << 10)
45 * P1020RDB-PD board has user selectable switches for evaluating different
46 * frequency and boot options for the P1020 device. The table that
47 * follow describe the available options. The front six binary number was in
48 * accordance with SW3[1:6].
49 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
50 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
51 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
52 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
53 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
54 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
55 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
57 #if defined(CONFIG_TARGET_P1020RDB_PD)
58 #define CONFIG_BOARDNAME "P1020RDB-PD"
59 #define CONFIG_NAND_FSL_ELBC
60 #define CONFIG_VSC7385_ENET
62 #define __SW_BOOT_MASK 0x03
63 #define __SW_BOOT_NOR 0x64
64 #define __SW_BOOT_SPI 0x34
65 #define __SW_BOOT_SD 0x24
66 #define __SW_BOOT_NAND 0x44
67 #define __SW_BOOT_PCIE 0x74
68 #define CONFIG_SYS_L2_SIZE (256 << 10)
70 * Dynamic MTD Partition support with mtdparts
74 #if defined(CONFIG_TARGET_P1021RDB)
75 #define CONFIG_BOARDNAME "P1021RDB-PC"
76 #define CONFIG_NAND_FSL_ELBC
78 #define CONFIG_VSC7385_ENET
79 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
80 addresses in the LBC */
81 #define __SW_BOOT_MASK 0x03
82 #define __SW_BOOT_NOR 0x5c
83 #define __SW_BOOT_SPI 0x1c
84 #define __SW_BOOT_SD 0x9c
85 #define __SW_BOOT_NAND 0xec
86 #define __SW_BOOT_PCIE 0x6c
87 #define CONFIG_SYS_L2_SIZE (256 << 10)
89 * Dynamic MTD Partition support with mtdparts
93 #if defined(CONFIG_TARGET_P1024RDB)
94 #define CONFIG_BOARDNAME "P1024RDB"
95 #define CONFIG_NAND_FSL_ELBC
97 #define __SW_BOOT_MASK 0xf3
98 #define __SW_BOOT_NOR 0x00
99 #define __SW_BOOT_SPI 0x08
100 #define __SW_BOOT_SD 0x04
101 #define __SW_BOOT_NAND 0x0c
102 #define CONFIG_SYS_L2_SIZE (256 << 10)
105 #if defined(CONFIG_TARGET_P1025RDB)
106 #define CONFIG_BOARDNAME "P1025RDB"
107 #define CONFIG_NAND_FSL_ELBC
111 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
112 addresses in the LBC */
113 #define __SW_BOOT_MASK 0xf3
114 #define __SW_BOOT_NOR 0x00
115 #define __SW_BOOT_SPI 0x08
116 #define __SW_BOOT_SD 0x04
117 #define __SW_BOOT_NAND 0x0c
118 #define CONFIG_SYS_L2_SIZE (256 << 10)
121 #if defined(CONFIG_TARGET_P2020RDB)
122 #define CONFIG_BOARDNAME "P2020RDB-PC"
123 #define CONFIG_NAND_FSL_ELBC
124 #define CONFIG_VSC7385_ENET
125 #define __SW_BOOT_MASK 0x03
126 #define __SW_BOOT_NOR 0xc8
127 #define __SW_BOOT_SPI 0x28
128 #define __SW_BOOT_SD 0x68 /* or 0x18 */
129 #define __SW_BOOT_NAND 0xe8
130 #define __SW_BOOT_PCIE 0xa8
131 #define CONFIG_SYS_L2_SIZE (512 << 10)
133 * Dynamic MTD Partition support with mtdparts
138 #define CONFIG_SPL_FLUSH_IMAGE
139 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
140 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
141 #define CONFIG_SPL_PAD_TO 0x20000
142 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
143 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
144 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
145 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
146 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
147 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
148 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
149 #define CONFIG_SPL_MMC_BOOT
150 #ifdef CONFIG_SPL_BUILD
151 #define CONFIG_SPL_COMMON_INIT_DDR
155 #ifdef CONFIG_SPIFLASH
156 #define CONFIG_SPL_SPI_FLASH_MINIMAL
157 #define CONFIG_SPL_FLUSH_IMAGE
158 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
159 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
160 #define CONFIG_SPL_PAD_TO 0x20000
161 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
162 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
163 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
164 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
165 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
166 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
167 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
168 #define CONFIG_SPL_SPI_BOOT
169 #ifdef CONFIG_SPL_BUILD
170 #define CONFIG_SPL_COMMON_INIT_DDR
175 #ifdef CONFIG_TPL_BUILD
176 #define CONFIG_SPL_NAND_BOOT
177 #define CONFIG_SPL_FLUSH_IMAGE
178 #define CONFIG_SPL_NAND_INIT
179 #define CONFIG_SPL_COMMON_INIT_DDR
180 #define CONFIG_SPL_MAX_SIZE (128 << 10)
181 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
182 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
183 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
184 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
185 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
186 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
187 #elif defined(CONFIG_SPL_BUILD)
188 #define CONFIG_SPL_INIT_MINIMAL
189 #define CONFIG_SPL_FLUSH_IMAGE
190 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
191 #define CONFIG_SPL_TEXT_BASE 0xff800000
192 #define CONFIG_SPL_MAX_SIZE 4096
193 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
194 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
195 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
196 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
197 #endif /* not CONFIG_TPL_BUILD */
199 #define CONFIG_SPL_PAD_TO 0x20000
200 #define CONFIG_TPL_PAD_TO 0x20000
201 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
202 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
205 #ifndef CONFIG_RESET_VECTOR_ADDRESS
206 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
209 #ifndef CONFIG_SYS_MONITOR_BASE
210 #ifdef CONFIG_SPL_BUILD
211 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
213 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
217 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
218 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
219 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
220 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
221 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
222 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
224 #define CONFIG_ENV_OVERWRITE
226 #define CONFIG_SYS_SATA_MAX_DEVICE 2
229 #if defined(CONFIG_TARGET_P2020RDB)
230 #define CONFIG_SYS_CLK_FREQ 100000000
232 #define CONFIG_SYS_CLK_FREQ 66666666
234 #define CONFIG_DDR_CLK_FREQ 66666666
236 #define CONFIG_HWCONFIG
238 * These can be toggled for performance analysis, otherwise use default.
240 #define CONFIG_L2_CACHE
243 #define CONFIG_ENABLE_36BIT_PHYS
245 #ifdef CONFIG_PHYS_64BIT
246 #define CONFIG_ADDR_MAP 1
247 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
250 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
251 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
253 #define CONFIG_SYS_CCSRBAR 0xffe00000
254 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
256 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
258 #ifdef CONFIG_SPL_BUILD
259 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
263 #define CONFIG_SYS_DDR_RAW_TIMING
264 #define CONFIG_DDR_SPD
265 #define CONFIG_SYS_SPD_BUS_NUM 1
266 #define SPD_EEPROM_ADDRESS 0x52
267 #undef CONFIG_FSL_DDR_INTERACTIVE
269 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
270 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
271 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
273 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
274 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
276 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
277 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
278 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
280 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
282 /* Default settings for DDR3 */
283 #ifndef CONFIG_TARGET_P2020RDB
284 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
285 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
286 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
287 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
288 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
289 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
291 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
292 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
293 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
294 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
296 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
297 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
298 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
299 #define CONFIG_SYS_DDR_RCW_1 0x00000000
300 #define CONFIG_SYS_DDR_RCW_2 0x00000000
301 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
302 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
303 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
304 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
306 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
307 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
308 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
309 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
310 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
311 #define CONFIG_SYS_DDR_MODE_1 0x40461520
312 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
313 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
316 #undef CONFIG_CLOCKS_IN_MHZ
321 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
322 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
323 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
324 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
326 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
327 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
328 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
329 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
330 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
331 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
332 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
336 * Local Bus Definitions
338 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
339 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
340 #define CONFIG_SYS_FLASH_BASE 0xec000000
341 #elif defined(CONFIG_TARGET_P1020UTM)
342 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
343 #define CONFIG_SYS_FLASH_BASE 0xee000000
345 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
346 #define CONFIG_SYS_FLASH_BASE 0xef000000
349 #ifdef CONFIG_PHYS_64BIT
350 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
352 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
355 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
358 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
360 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
361 #define CONFIG_SYS_FLASH_QUIET_TEST
362 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
364 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
366 #undef CONFIG_SYS_FLASH_CHECKSUM
367 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
368 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
370 #define CONFIG_SYS_FLASH_EMPTY_INFO
373 #ifdef CONFIG_NAND_FSL_ELBC
374 #define CONFIG_SYS_NAND_BASE 0xff800000
375 #ifdef CONFIG_PHYS_64BIT
376 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
378 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
381 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
382 #define CONFIG_SYS_MAX_NAND_DEVICE 1
383 #if defined(CONFIG_TARGET_P1020RDB_PD)
384 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
386 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
389 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
390 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
391 | BR_PS_8 /* Port Size = 8 bit */ \
392 | BR_MS_FCM /* MSEL = FCM */ \
394 #if defined(CONFIG_TARGET_P1020RDB_PD)
395 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
396 | OR_FCM_PGS /* Large Page*/ \
404 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
412 #endif /* CONFIG_NAND_FSL_ELBC */
414 #define CONFIG_SYS_INIT_RAM_LOCK
415 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
416 #ifdef CONFIG_PHYS_64BIT
417 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
418 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
419 /* The assembler doesn't like typecast */
420 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
421 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
422 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
424 /* Initial L1 address */
425 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
426 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
427 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
429 /* Size of used area in RAM */
430 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
432 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
433 GENERATED_GBL_DATA_SIZE)
434 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
436 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
437 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
439 #define CONFIG_SYS_CPLD_BASE 0xffa00000
440 #ifdef CONFIG_PHYS_64BIT
441 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
443 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
445 /* CPLD config size: 1Mb */
446 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
448 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
450 #define CONFIG_SYS_PMC_BASE 0xff980000
451 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
452 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
454 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
455 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
459 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
460 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
461 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
462 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
464 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
465 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
466 #ifdef CONFIG_NAND_FSL_ELBC
467 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
468 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
471 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
472 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
475 #ifdef CONFIG_VSC7385_ENET
476 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
478 #ifdef CONFIG_PHYS_64BIT
479 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
481 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
484 #define CONFIG_SYS_VSC7385_BR_PRELIM \
485 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
486 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
487 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
488 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
490 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
491 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
493 /* The size of the VSC7385 firmware image */
494 #define CONFIG_VSC7385_IMAGE_SIZE 8192
498 * Config the L2 Cache as L2 SRAM
500 #if defined(CONFIG_SPL_BUILD)
501 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
502 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
503 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
504 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
505 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
506 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
507 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
508 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
509 #if defined(CONFIG_TARGET_P2020RDB)
510 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
512 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
514 #elif defined(CONFIG_NAND)
515 #ifdef CONFIG_TPL_BUILD
516 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
517 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
518 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
519 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
520 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
521 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
522 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
523 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
525 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
526 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
527 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
528 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
529 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
530 #endif /* CONFIG_TPL_BUILD */
534 /* Serial Port - controlled on board with jumper J8
538 #undef CONFIG_SERIAL_SOFTWARE_FIFO
539 #define CONFIG_SYS_NS16550_SERIAL
540 #define CONFIG_SYS_NS16550_REG_SIZE 1
541 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
542 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
543 #define CONFIG_NS16550_MIN_FUNCTIONS
546 #define CONFIG_SYS_BAUDRATE_TABLE \
547 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
549 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
550 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
553 #define CONFIG_SYS_I2C
554 #define CONFIG_SYS_I2C_FSL
555 #define CONFIG_SYS_FSL_I2C_SPEED 400000
556 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
557 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
558 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
559 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
560 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
561 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
562 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
563 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
568 #undef CONFIG_ID_EEPROM
570 #define CONFIG_RTC_PT7C4338
571 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
572 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
574 /* enable read and write access to EEPROM */
575 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
576 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
577 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
580 * eSPI - Enhanced SPI
582 #define CONFIG_HARD_SPI
584 #if defined(CONFIG_SPI_FLASH)
585 #define CONFIG_SF_DEFAULT_SPEED 10000000
586 #define CONFIG_SF_DEFAULT_MODE 0
589 #if defined(CONFIG_PCI)
592 * Memory space is mapped 1-1, but I/O space must start from 0.
595 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
596 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
597 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
598 #ifdef CONFIG_PHYS_64BIT
599 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
600 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
602 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
603 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
605 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
606 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
607 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
608 #ifdef CONFIG_PHYS_64BIT
609 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
611 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
613 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
615 /* controller 1, Slot 2, tgtid 1, Base address a000 */
616 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
617 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
618 #ifdef CONFIG_PHYS_64BIT
619 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
620 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
622 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
623 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
625 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
626 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
627 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
628 #ifdef CONFIG_PHYS_64BIT
629 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
631 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
633 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
635 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
636 #endif /* CONFIG_PCI */
638 #if defined(CONFIG_TSEC_ENET)
640 #define CONFIG_TSEC1_NAME "eTSEC1"
642 #define CONFIG_TSEC2_NAME "eTSEC2"
644 #define CONFIG_TSEC3_NAME "eTSEC3"
646 #define TSEC1_PHY_ADDR 2
647 #define TSEC2_PHY_ADDR 0
648 #define TSEC3_PHY_ADDR 1
650 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
651 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
652 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
654 #define TSEC1_PHYIDX 0
655 #define TSEC2_PHYIDX 0
656 #define TSEC3_PHYIDX 0
658 #define CONFIG_ETHPRIME "eTSEC1"
660 #define CONFIG_HAS_ETH0
661 #define CONFIG_HAS_ETH1
662 #define CONFIG_HAS_ETH2
663 #endif /* CONFIG_TSEC_ENET */
666 /* QE microcode/firmware address */
667 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
668 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
669 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
670 #endif /* CONFIG_QE */
672 #ifdef CONFIG_TARGET_P1025RDB
674 * QE UEC ethernet configuration
676 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
678 #undef CONFIG_UEC_ETH
679 #define CONFIG_PHY_MODE_NEED_CHANGE
681 #define CONFIG_UEC_ETH1 /* ETH1 */
682 #define CONFIG_HAS_ETH0
684 #ifdef CONFIG_UEC_ETH1
685 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
686 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
687 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
688 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
689 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
690 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
691 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
692 #endif /* CONFIG_UEC_ETH1 */
694 #define CONFIG_UEC_ETH5 /* ETH5 */
695 #define CONFIG_HAS_ETH1
697 #ifdef CONFIG_UEC_ETH5
698 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
699 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
700 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
701 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
702 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
703 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
704 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
705 #endif /* CONFIG_UEC_ETH5 */
706 #endif /* CONFIG_TARGET_P1025RDB */
711 #ifdef CONFIG_SPIFLASH
712 #define CONFIG_ENV_SPI_BUS 0
713 #define CONFIG_ENV_SPI_CS 0
714 #define CONFIG_ENV_SPI_MAX_HZ 10000000
715 #define CONFIG_ENV_SPI_MODE 0
716 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
717 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
718 #define CONFIG_ENV_SECT_SIZE 0x10000
719 #elif defined(CONFIG_SDCARD)
720 #define CONFIG_FSL_FIXED_MMC_LOCATION
721 #define CONFIG_ENV_SIZE 0x2000
722 #define CONFIG_SYS_MMC_ENV_DEV 0
723 #elif defined(CONFIG_NAND)
724 #ifdef CONFIG_TPL_BUILD
725 #define CONFIG_ENV_SIZE 0x2000
726 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
728 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
730 #define CONFIG_ENV_OFFSET (1024 * 1024)
731 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
732 #elif defined(CONFIG_SYS_RAMBOOT)
733 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
734 #define CONFIG_ENV_SIZE 0x2000
736 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
737 #define CONFIG_ENV_SIZE 0x2000
738 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
741 #define CONFIG_LOADS_ECHO /* echo on for serial download */
742 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
747 #define CONFIG_HAS_FSL_DR_USB
749 #if defined(CONFIG_HAS_FSL_DR_USB)
750 #ifdef CONFIG_USB_EHCI_HCD
751 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
752 #define CONFIG_USB_EHCI_FSL
756 #if defined(CONFIG_TARGET_P1020RDB_PD)
757 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
761 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
764 #undef CONFIG_WATCHDOG /* watchdog disabled */
767 * Miscellaneous configurable options
769 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
772 * For booting Linux, the board info and command line data
773 * have to be in the first 64 MB of memory, since this is
774 * the maximum mapped by the Linux kernel during initialization.
776 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
777 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
779 #if defined(CONFIG_CMD_KGDB)
780 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
784 * Environment Configuration
786 #define CONFIG_HOSTNAME "unknown"
787 #define CONFIG_ROOTPATH "/opt/nfsroot"
788 #define CONFIG_BOOTFILE "uImage"
789 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
791 /* default location for tftp and bootm */
792 #define CONFIG_LOADADDR 1000000
795 #define __NOR_RST_CMD \
796 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
797 i2c mw 18 3 __SW_BOOT_MASK 1; reset
800 #define __SPI_RST_CMD \
801 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
802 i2c mw 18 3 __SW_BOOT_MASK 1; reset
805 #define __SD_RST_CMD \
806 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
807 i2c mw 18 3 __SW_BOOT_MASK 1; reset
809 #ifdef __SW_BOOT_NAND
810 #define __NAND_RST_CMD \
811 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
812 i2c mw 18 3 __SW_BOOT_MASK 1; reset
814 #ifdef __SW_BOOT_PCIE
815 #define __PCIE_RST_CMD \
816 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
817 i2c mw 18 3 __SW_BOOT_MASK 1; reset
820 #define CONFIG_EXTRA_ENV_SETTINGS \
822 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
823 "loadaddr=1000000\0" \
824 "bootfile=uImage\0" \
825 "tftpflash=tftpboot $loadaddr $uboot; " \
826 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
827 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
828 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
829 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
830 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
831 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
832 "consoledev=ttyS0\0" \
833 "ramdiskaddr=2000000\0" \
834 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
835 "fdtaddr=1e00000\0" \
837 "jffs2nor=mtdblock3\0" \
838 "norbootaddr=ef080000\0" \
839 "norfdtaddr=ef040000\0" \
840 "jffs2nand=mtdblock9\0" \
841 "nandbootaddr=100000\0" \
842 "nandfdtaddr=80000\0" \
843 "ramdisk_size=120000\0" \
844 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
845 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
846 __stringify(__NOR_RST_CMD)"\0" \
847 __stringify(__SPI_RST_CMD)"\0" \
848 __stringify(__SD_RST_CMD)"\0" \
849 __stringify(__NAND_RST_CMD)"\0" \
850 __stringify(__PCIE_RST_CMD)"\0"
852 #define CONFIG_NFSBOOTCOMMAND \
853 "setenv bootargs root=/dev/nfs rw " \
854 "nfsroot=$serverip:$rootpath " \
855 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
856 "console=$consoledev,$baudrate $othbootargs;" \
857 "tftp $loadaddr $bootfile;" \
858 "tftp $fdtaddr $fdtfile;" \
859 "bootm $loadaddr - $fdtaddr"
861 #define CONFIG_HDBOOT \
862 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
863 "console=$consoledev,$baudrate $othbootargs;" \
865 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
866 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
867 "bootm $loadaddr - $fdtaddr"
869 #define CONFIG_USB_FAT_BOOT \
870 "setenv bootargs root=/dev/ram rw " \
871 "console=$consoledev,$baudrate $othbootargs " \
872 "ramdisk_size=$ramdisk_size;" \
874 "fatload usb 0:2 $loadaddr $bootfile;" \
875 "fatload usb 0:2 $fdtaddr $fdtfile;" \
876 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
877 "bootm $loadaddr $ramdiskaddr $fdtaddr"
879 #define CONFIG_USB_EXT2_BOOT \
880 "setenv bootargs root=/dev/ram rw " \
881 "console=$consoledev,$baudrate $othbootargs " \
882 "ramdisk_size=$ramdisk_size;" \
884 "ext2load usb 0:4 $loadaddr $bootfile;" \
885 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
886 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
887 "bootm $loadaddr $ramdiskaddr $fdtaddr"
889 #define CONFIG_NORBOOT \
890 "setenv bootargs root=/dev/$jffs2nor rw " \
891 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
892 "bootm $norbootaddr - $norfdtaddr"
894 #define CONFIG_RAMBOOTCOMMAND \
895 "setenv bootargs root=/dev/ram rw " \
896 "console=$consoledev,$baudrate $othbootargs " \
897 "ramdisk_size=$ramdisk_size;" \
898 "tftp $ramdiskaddr $ramdiskfile;" \
899 "tftp $loadaddr $bootfile;" \
900 "tftp $fdtaddr $fdtfile;" \
901 "bootm $loadaddr $ramdiskaddr $fdtaddr"
903 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
905 #endif /* __CONFIG_H */