1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * QorIQ RDB boards configuration file
13 #include <linux/stringify.h>
15 #if defined(CONFIG_TARGET_P1020RDB_PC)
16 #define CONFIG_VSC7385_ENET
18 #define __SW_BOOT_MASK 0x03
19 #define __SW_BOOT_NOR 0x5c
20 #define __SW_BOOT_SPI 0x1c
21 #define __SW_BOOT_SD 0x9c
22 #define __SW_BOOT_NAND 0xec
23 #define __SW_BOOT_PCIE 0x6c
24 #define __SW_NOR_BANK_MASK 0xfd
25 #define __SW_NOR_BANK_UP 0x00
26 #define __SW_NOR_BANK_LO 0x02
27 #define __SW_BOOT_NOR_BANK_UP 0x5c /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
28 #define __SW_BOOT_NOR_BANK_LO 0x5e /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
29 #define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
33 * P1020RDB-PD board has user selectable switches for evaluating different
34 * frequency and boot options for the P1020 device. The table that
35 * follow describe the available options. The front six binary number was in
36 * accordance with SW3[1:6].
37 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
38 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
39 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
40 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
41 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
42 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
43 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
45 #if defined(CONFIG_TARGET_P1020RDB_PD)
46 #define CONFIG_VSC7385_ENET
48 #define __SW_BOOT_MASK 0x03
49 #define __SW_BOOT_NOR 0x64
50 #define __SW_BOOT_SPI 0x34
51 #define __SW_BOOT_SD 0x24
52 #define __SW_BOOT_NAND 0x44
53 #define __SW_BOOT_PCIE 0x74
54 #define __SW_NOR_BANK_MASK 0xfd
55 #define __SW_NOR_BANK_UP 0x00
56 #define __SW_NOR_BANK_LO 0x02
57 #define __SW_BOOT_NOR_BANK_UP 0x64 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
58 #define __SW_BOOT_NOR_BANK_LO 0x66 /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
59 #define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
61 * Dynamic MTD Partition support with mtdparts
65 #if defined(CONFIG_TARGET_P2020RDB)
66 #define CONFIG_VSC7385_ENET
67 #define __SW_BOOT_MASK 0x03
68 #define __SW_BOOT_NOR 0xc8
69 #define __SW_BOOT_SPI 0x28
70 #define __SW_BOOT_SD 0x68
71 #define __SW_BOOT_SD2 0x18
72 #define __SW_BOOT_NAND 0xe8
73 #define __SW_BOOT_PCIE 0xa8
74 #define __SW_NOR_BANK_MASK 0xfd
75 #define __SW_NOR_BANK_UP 0x00
76 #define __SW_NOR_BANK_LO 0x02
77 #define __SW_BOOT_NOR_BANK_UP 0xc8 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
78 #define __SW_BOOT_NOR_BANK_LO 0xca /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
79 #define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
81 * Dynamic MTD Partition support with mtdparts
86 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
87 #define CONFIG_SYS_MMC_U_BOOT_DST CONFIG_TEXT_BASE
88 #define CONFIG_SYS_MMC_U_BOOT_START CONFIG_TEXT_BASE
89 #ifdef CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR
90 #define CONFIG_SYS_MMC_U_BOOT_OFFS (CONFIG_SPL_PAD_TO - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA*512)
92 #define CONFIG_SYS_MMC_U_BOOT_OFFS CONFIG_SPL_PAD_TO
94 #elif defined(CONFIG_SPIFLASH)
95 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
96 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_TEXT_BASE
97 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START CONFIG_TEXT_BASE
98 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SPL_PAD_TO
99 #elif defined(CONFIG_MTD_RAW_NAND)
100 #ifdef CONFIG_TPL_BUILD
101 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
102 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
103 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
104 #elif defined(CONFIG_SPL_BUILD)
105 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
106 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
107 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
108 #endif /* not CONFIG_TPL_BUILD */
111 #ifndef CONFIG_RESET_VECTOR_ADDRESS
112 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
115 #define CONFIG_HWCONFIG
117 * These can be toggled for performance analysis, otherwise use default.
119 #define CONFIG_L2_CACHE
121 #define CONFIG_SYS_CCSRBAR 0xffe00000
122 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
125 #define SPD_EEPROM_ADDRESS 0x52
127 #if defined(CONFIG_TARGET_P1020RDB_PD)
128 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
130 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
132 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
133 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
134 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
136 /* Default settings for DDR3 */
137 #ifndef CONFIG_TARGET_P2020RDB
138 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
139 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
140 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
141 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
142 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
143 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
145 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
146 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
147 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
149 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
150 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
151 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
152 #define CONFIG_SYS_DDR_RCW_1 0x00000000
153 #define CONFIG_SYS_DDR_RCW_2 0x00000000
154 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
155 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
156 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
157 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
159 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
160 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
161 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
162 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
163 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
164 #define CONFIG_SYS_DDR_MODE_1 0x40461520
165 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
166 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
172 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
173 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
174 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
175 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
177 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
178 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
179 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
180 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
181 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
182 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
186 * Local Bus Definitions
188 #if defined(CONFIG_TARGET_P1020RDB_PD)
189 #define CONFIG_SYS_FLASH_BASE 0xec000000
191 #define CONFIG_SYS_FLASH_BASE 0xef000000
194 #ifdef CONFIG_PHYS_64BIT
195 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
197 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
200 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
203 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
205 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
206 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
209 #ifdef CONFIG_NAND_FSL_ELBC
210 #define CONFIG_SYS_NAND_BASE 0xff800000
211 #ifdef CONFIG_PHYS_64BIT
212 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
214 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
217 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
219 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
220 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
221 | BR_PS_8 /* Port Size = 8 bit */ \
222 | BR_MS_FCM /* MSEL = FCM */ \
224 #if defined(CONFIG_TARGET_P1020RDB_PD)
225 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
226 | OR_FCM_PGS /* Large Page*/ \
234 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
242 #endif /* CONFIG_NAND_FSL_ELBC */
244 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
245 #ifdef CONFIG_PHYS_64BIT
246 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
247 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
248 /* The assembler doesn't like typecast */
249 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
250 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
251 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
253 /* Initial L1 address */
254 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
255 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
256 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
258 /* Size of used area in RAM */
259 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
261 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
263 #define CONFIG_SYS_CPLD_BASE 0xffa00000
264 #ifdef CONFIG_PHYS_64BIT
265 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
267 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
269 /* CPLD config size: 1Mb */
272 #ifdef CONFIG_VSC7385_ENET
273 #define __VSCFW_ADDR "vscfw_addr=ef000000\0"
274 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
276 #ifdef CONFIG_PHYS_64BIT
277 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
279 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
282 #define CONFIG_SYS_VSC7385_BR_PRELIM \
283 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
284 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
285 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
286 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
288 /* The size of the VSC7385 firmware image */
289 #define CONFIG_VSC7385_IMAGE_SIZE 8192
293 #define __VSCFW_ADDR ""
297 * Config the L2 Cache as L2 SRAM
299 #if defined(CONFIG_SPL_BUILD)
300 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
301 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
302 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
303 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
304 #elif defined(CONFIG_MTD_RAW_NAND)
305 #ifdef CONFIG_TPL_BUILD
306 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
307 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
308 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
310 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
311 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
312 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
313 #endif /* CONFIG_TPL_BUILD */
317 /* Serial Port - controlled on board with jumper J8
321 #undef CONFIG_SERIAL_SOFTWARE_FIFO
322 #define CONFIG_SYS_NS16550_SERIAL
323 #define CONFIG_SYS_NS16550_REG_SIZE 1
324 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
325 #if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)
326 #define CONFIG_NS16550_MIN_FUNCTIONS
329 #define CONFIG_SYS_BAUDRATE_TABLE \
330 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
332 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
333 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
336 #if !CONFIG_IS_ENABLED(DM_I2C)
337 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
344 #define CONFIG_RTC_PT7C4338
345 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
346 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
348 /* enable read and write access to EEPROM */
350 #if defined(CONFIG_PCI)
353 * Memory space is mapped 1-1, but I/O space must start from 0.
356 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
357 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
358 #ifdef CONFIG_PHYS_64BIT
359 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
361 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
363 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
364 #ifdef CONFIG_PHYS_64BIT
365 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
367 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
370 /* controller 1, Slot 2, tgtid 1, Base address a000 */
371 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
372 #ifdef CONFIG_PHYS_64BIT
373 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
375 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
377 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
378 #ifdef CONFIG_PHYS_64BIT
379 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
381 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
383 #endif /* CONFIG_PCI */
385 #if defined(CONFIG_TSEC_ENET)
387 #define CONFIG_TSEC1_NAME "eTSEC1"
389 #define CONFIG_TSEC2_NAME "eTSEC2"
391 #define CONFIG_TSEC3_NAME "eTSEC3"
393 #define TSEC1_PHY_ADDR 2
394 #define TSEC2_PHY_ADDR 0
395 #define TSEC3_PHY_ADDR 1
397 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
398 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
399 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
401 #define TSEC1_PHYIDX 0
402 #define TSEC2_PHYIDX 0
403 #define TSEC3_PHYIDX 0
404 #endif /* CONFIG_TSEC_ENET */
409 #if defined(CONFIG_MTD_RAW_NAND)
410 #ifdef CONFIG_TPL_BUILD
411 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
420 #define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
424 * Miscellaneous configurable options
428 * For booting Linux, the board info and command line data
429 * have to be in the first 64 MB of memory, since this is
430 * the maximum mapped by the Linux kernel during initialization.
432 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
435 * Environment Configuration
437 #define CONFIG_HOSTNAME "unknown"
438 #define CONFIG_ROOTPATH "/opt/nfsroot"
439 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
441 #include "p1_p2_bootsrc.h"
443 #define CONFIG_EXTRA_ENV_SETTINGS \
445 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
446 "loadaddr=1000000\0" \
447 "bootfile=uImage\0" \
448 "tftpflash=tftpboot $loadaddr $uboot; " \
449 "protect off " __stringify(CONFIG_TEXT_BASE) " +$filesize; " \
450 "erase " __stringify(CONFIG_TEXT_BASE) " +$filesize; " \
451 "cp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) " $filesize; " \
452 "protect on " __stringify(CONFIG_TEXT_BASE) " +$filesize; " \
453 "cmp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) " $filesize\0" \
454 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
455 "consoledev=ttyS0\0" \
456 "ramdiskaddr=2000000\0" \
457 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
458 "fdtaddr=1e00000\0" \
460 "jffs2nor=mtdblock3\0" \
461 "norbootaddr=ef080000\0" \
462 "norfdtaddr=ef040000\0" \
463 "jffs2nand=mtdblock9\0" \
464 "nandbootaddr=100000\0" \
465 "nandfdtaddr=80000\0" \
466 "ramdisk_size=120000\0" \
468 MAP_NOR_LO_CMD(map_lowernorbank) \
469 MAP_NOR_UP_CMD(map_uppernorbank) \
470 RST_NOR_CMD(norboot) \
471 RST_NOR_LO_CMD(norlowerboot) \
472 RST_NOR_UP_CMD(norupperboot) \
473 RST_SPI_CMD(spiboot) \
475 RST_SD2_CMD(sd2boot) \
476 RST_NAND_CMD(nandboot) \
477 RST_PCIE_CMD(pciboot) \
478 RST_DEF_CMD(defboot) \
481 #define CONFIG_USB_FAT_BOOT \
482 "setenv bootargs root=/dev/ram rw " \
483 "console=$consoledev,$baudrate $othbootargs " \
484 "ramdisk_size=$ramdisk_size;" \
486 "fatload usb 0:2 $loadaddr $bootfile;" \
487 "fatload usb 0:2 $fdtaddr $fdtfile;" \
488 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
489 "bootm $loadaddr $ramdiskaddr $fdtaddr"
491 #define CONFIG_USB_EXT2_BOOT \
492 "setenv bootargs root=/dev/ram rw " \
493 "console=$consoledev,$baudrate $othbootargs " \
494 "ramdisk_size=$ramdisk_size;" \
496 "ext2load usb 0:4 $loadaddr $bootfile;" \
497 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
498 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
499 "bootm $loadaddr $ramdiskaddr $fdtaddr"
501 #define CONFIG_NORBOOT \
502 "setenv bootargs root=/dev/$jffs2nor rw " \
503 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
504 "bootm $norbootaddr - $norfdtaddr"
506 #endif /* __CONFIG_H */