1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * QorIQ RDB boards configuration file
13 #include <linux/stringify.h>
15 #if defined(CONFIG_TARGET_P1020MBG)
16 #define CONFIG_BOARDNAME "P1020MBG-PC"
17 #define CONFIG_VSC7385_ENET
19 #define __SW_BOOT_MASK 0x03
20 #define __SW_BOOT_NOR 0xe4
21 #define __SW_BOOT_SD 0x54
22 #define CONFIG_SYS_L2_SIZE (256 << 10)
25 #if defined(CONFIG_TARGET_P1020UTM)
26 #define CONFIG_BOARDNAME "P1020UTM-PC"
27 #define __SW_BOOT_MASK 0x03
28 #define __SW_BOOT_NOR 0xe0
29 #define __SW_BOOT_SD 0x50
30 #define CONFIG_SYS_L2_SIZE (256 << 10)
33 #if defined(CONFIG_TARGET_P1020RDB_PC)
34 #define CONFIG_BOARDNAME "P1020RDB-PC"
35 #define CONFIG_NAND_FSL_ELBC
36 #define CONFIG_VSC7385_ENET
38 #define __SW_BOOT_MASK 0x03
39 #define __SW_BOOT_NOR 0x5c
40 #define __SW_BOOT_SPI 0x1c
41 #define __SW_BOOT_SD 0x9c
42 #define __SW_BOOT_NAND 0xec
43 #define __SW_BOOT_PCIE 0x6c
44 #define CONFIG_SYS_L2_SIZE (256 << 10)
48 * P1020RDB-PD board has user selectable switches for evaluating different
49 * frequency and boot options for the P1020 device. The table that
50 * follow describe the available options. The front six binary number was in
51 * accordance with SW3[1:6].
52 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
53 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
54 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
55 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
56 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
57 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
58 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
60 #if defined(CONFIG_TARGET_P1020RDB_PD)
61 #define CONFIG_BOARDNAME "P1020RDB-PD"
62 #define CONFIG_NAND_FSL_ELBC
63 #define CONFIG_VSC7385_ENET
65 #define __SW_BOOT_MASK 0x03
66 #define __SW_BOOT_NOR 0x64
67 #define __SW_BOOT_SPI 0x34
68 #define __SW_BOOT_SD 0x24
69 #define __SW_BOOT_NAND 0x44
70 #define __SW_BOOT_PCIE 0x74
71 #define CONFIG_SYS_L2_SIZE (256 << 10)
73 * Dynamic MTD Partition support with mtdparts
77 #if defined(CONFIG_TARGET_P1021RDB)
78 #define CONFIG_BOARDNAME "P1021RDB-PC"
79 #define CONFIG_NAND_FSL_ELBC
80 #define CONFIG_VSC7385_ENET
81 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
82 addresses in the LBC */
83 #define __SW_BOOT_MASK 0x03
84 #define __SW_BOOT_NOR 0x5c
85 #define __SW_BOOT_SPI 0x1c
86 #define __SW_BOOT_SD 0x9c
87 #define __SW_BOOT_NAND 0xec
88 #define __SW_BOOT_PCIE 0x6c
89 #define CONFIG_SYS_L2_SIZE (256 << 10)
91 * Dynamic MTD Partition support with mtdparts
95 #if defined(CONFIG_TARGET_P1024RDB)
96 #define CONFIG_BOARDNAME "P1024RDB"
97 #define CONFIG_NAND_FSL_ELBC
99 #define __SW_BOOT_MASK 0xf3
100 #define __SW_BOOT_NOR 0x00
101 #define __SW_BOOT_SPI 0x08
102 #define __SW_BOOT_SD 0x04
103 #define __SW_BOOT_NAND 0x0c
104 #define CONFIG_SYS_L2_SIZE (256 << 10)
107 #if defined(CONFIG_TARGET_P1025RDB)
108 #define CONFIG_BOARDNAME "P1025RDB"
109 #define CONFIG_NAND_FSL_ELBC
112 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
113 addresses in the LBC */
114 #define __SW_BOOT_MASK 0xf3
115 #define __SW_BOOT_NOR 0x00
116 #define __SW_BOOT_SPI 0x08
117 #define __SW_BOOT_SD 0x04
118 #define __SW_BOOT_NAND 0x0c
119 #define CONFIG_SYS_L2_SIZE (256 << 10)
122 #if defined(CONFIG_TARGET_P2020RDB)
123 #define CONFIG_BOARDNAME "P2020RDB-PC"
124 #define CONFIG_NAND_FSL_ELBC
125 #define CONFIG_VSC7385_ENET
126 #define __SW_BOOT_MASK 0x03
127 #define __SW_BOOT_NOR 0xc8
128 #define __SW_BOOT_SPI 0x28
129 #define __SW_BOOT_SD 0x68 /* or 0x18 */
130 #define __SW_BOOT_NAND 0xe8
131 #define __SW_BOOT_PCIE 0xa8
132 #define CONFIG_SYS_L2_SIZE (512 << 10)
134 * Dynamic MTD Partition support with mtdparts
139 #define CONFIG_SPL_FLUSH_IMAGE
140 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
141 #define CONFIG_SPL_PAD_TO 0x20000
142 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
143 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
144 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
145 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
146 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
147 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
148 #ifdef CONFIG_SPL_BUILD
149 #define CONFIG_SPL_COMMON_INIT_DDR
153 #ifdef CONFIG_SPIFLASH
154 #define CONFIG_SPL_SPI_FLASH_MINIMAL
155 #define CONFIG_SPL_FLUSH_IMAGE
156 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
157 #define CONFIG_SPL_PAD_TO 0x20000
158 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
159 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
160 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
161 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
162 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
163 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
164 #ifdef CONFIG_SPL_BUILD
165 #define CONFIG_SPL_COMMON_INIT_DDR
169 #ifdef CONFIG_MTD_RAW_NAND
170 #ifdef CONFIG_TPL_BUILD
171 #define CONFIG_SPL_FLUSH_IMAGE
172 #define CONFIG_SPL_NAND_INIT
173 #define CONFIG_SPL_COMMON_INIT_DDR
174 #define CONFIG_SPL_MAX_SIZE (128 << 10)
175 #define CONFIG_TPL_TEXT_BASE 0xf8f81000
176 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
177 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
178 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
179 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
180 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
181 #elif defined(CONFIG_SPL_BUILD)
182 #define CONFIG_SPL_INIT_MINIMAL
183 #define CONFIG_SPL_FLUSH_IMAGE
184 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
185 #define CONFIG_SPL_MAX_SIZE 4096
186 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
187 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
188 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
189 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
190 #endif /* not CONFIG_TPL_BUILD */
192 #define CONFIG_SPL_PAD_TO 0x20000
193 #define CONFIG_TPL_PAD_TO 0x20000
194 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
197 #ifndef CONFIG_RESET_VECTOR_ADDRESS
198 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
201 #ifndef CONFIG_SYS_MONITOR_BASE
202 #ifdef CONFIG_TPL_BUILD
203 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
204 #elif defined(CONFIG_SPL_BUILD)
205 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
207 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
211 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
212 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
213 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
215 #define CONFIG_ENV_OVERWRITE
217 #define CONFIG_SYS_SATA_MAX_DEVICE 2
220 #if defined(CONFIG_TARGET_P2020RDB)
221 #define CONFIG_SYS_CLK_FREQ 100000000
223 #define CONFIG_SYS_CLK_FREQ 66666666
225 #define CONFIG_DDR_CLK_FREQ 66666666
227 #define CONFIG_HWCONFIG
229 * These can be toggled for performance analysis, otherwise use default.
231 #define CONFIG_L2_CACHE
234 #define CONFIG_ENABLE_36BIT_PHYS
236 #ifdef CONFIG_PHYS_64BIT
237 #define CONFIG_ADDR_MAP 1
238 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
241 #define CONFIG_SYS_CCSRBAR 0xffe00000
242 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
244 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
246 #ifdef CONFIG_SPL_BUILD
247 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
251 #define CONFIG_SYS_DDR_RAW_TIMING
252 #define CONFIG_DDR_SPD
253 #define CONFIG_SYS_SPD_BUS_NUM 1
254 #define SPD_EEPROM_ADDRESS 0x52
256 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
257 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
258 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
260 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
261 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
263 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
264 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
265 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
267 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
269 /* Default settings for DDR3 */
270 #ifndef CONFIG_TARGET_P2020RDB
271 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
272 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
273 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
274 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
275 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
276 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
278 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
279 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
280 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
281 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
283 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
284 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
285 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
286 #define CONFIG_SYS_DDR_RCW_1 0x00000000
287 #define CONFIG_SYS_DDR_RCW_2 0x00000000
288 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
289 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
290 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
291 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
293 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
294 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
295 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
296 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
297 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
298 #define CONFIG_SYS_DDR_MODE_1 0x40461520
299 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
300 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
306 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
307 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
308 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
309 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
311 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
312 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
313 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
314 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
315 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
316 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
317 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
321 * Local Bus Definitions
323 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
324 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
325 #define CONFIG_SYS_FLASH_BASE 0xec000000
326 #elif defined(CONFIG_TARGET_P1020UTM)
327 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
328 #define CONFIG_SYS_FLASH_BASE 0xee000000
330 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
331 #define CONFIG_SYS_FLASH_BASE 0xef000000
334 #ifdef CONFIG_PHYS_64BIT
335 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
337 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
340 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
343 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
345 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
346 #define CONFIG_SYS_FLASH_QUIET_TEST
347 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
349 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
351 #undef CONFIG_SYS_FLASH_CHECKSUM
352 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
353 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
355 #define CONFIG_SYS_FLASH_EMPTY_INFO
358 #ifdef CONFIG_NAND_FSL_ELBC
359 #define CONFIG_SYS_NAND_BASE 0xff800000
360 #ifdef CONFIG_PHYS_64BIT
361 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
363 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
366 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
367 #define CONFIG_SYS_MAX_NAND_DEVICE 1
368 #if defined(CONFIG_TARGET_P1020RDB_PD)
369 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
371 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
374 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
375 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
376 | BR_PS_8 /* Port Size = 8 bit */ \
377 | BR_MS_FCM /* MSEL = FCM */ \
379 #if defined(CONFIG_TARGET_P1020RDB_PD)
380 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
381 | OR_FCM_PGS /* Large Page*/ \
389 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
397 #endif /* CONFIG_NAND_FSL_ELBC */
399 #define CONFIG_SYS_INIT_RAM_LOCK
400 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
401 #ifdef CONFIG_PHYS_64BIT
402 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
403 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
404 /* The assembler doesn't like typecast */
405 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
406 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
407 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
409 /* Initial L1 address */
410 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
411 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
412 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
414 /* Size of used area in RAM */
415 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
417 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
418 GENERATED_GBL_DATA_SIZE)
419 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
421 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
422 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
424 #define CONFIG_SYS_CPLD_BASE 0xffa00000
425 #ifdef CONFIG_PHYS_64BIT
426 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
428 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
430 /* CPLD config size: 1Mb */
431 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
433 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
435 #define CONFIG_SYS_PMC_BASE 0xff980000
436 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
437 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
439 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
440 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
443 #ifdef CONFIG_MTD_RAW_NAND
444 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
445 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
446 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
447 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
449 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
450 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
451 #ifdef CONFIG_NAND_FSL_ELBC
452 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
453 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
456 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
457 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
460 #ifdef CONFIG_VSC7385_ENET
461 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
463 #ifdef CONFIG_PHYS_64BIT
464 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
466 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
469 #define CONFIG_SYS_VSC7385_BR_PRELIM \
470 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
471 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
472 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
473 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
475 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
476 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
478 /* The size of the VSC7385 firmware image */
479 #define CONFIG_VSC7385_IMAGE_SIZE 8192
483 * Config the L2 Cache as L2 SRAM
485 #if defined(CONFIG_SPL_BUILD)
486 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
487 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
488 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
489 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
490 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
491 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
492 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
493 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
494 #if defined(CONFIG_TARGET_P2020RDB)
495 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
497 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
499 #elif defined(CONFIG_MTD_RAW_NAND)
500 #ifdef CONFIG_TPL_BUILD
501 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
502 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
503 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
504 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
505 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
506 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
507 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
508 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
510 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
511 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
512 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
513 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
514 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
515 #endif /* CONFIG_TPL_BUILD */
519 /* Serial Port - controlled on board with jumper J8
523 #undef CONFIG_SERIAL_SOFTWARE_FIFO
524 #define CONFIG_SYS_NS16550_SERIAL
525 #define CONFIG_SYS_NS16550_REG_SIZE 1
526 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
527 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
528 #define CONFIG_NS16550_MIN_FUNCTIONS
531 #define CONFIG_SYS_BAUDRATE_TABLE \
532 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
534 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
535 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
538 #ifndef CONFIG_DM_I2C
539 #define CONFIG_SYS_I2C
540 #define CONFIG_SYS_FSL_I2C_SPEED 400000
541 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
542 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
543 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
544 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
545 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
546 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
548 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
549 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
552 #define CONFIG_SYS_I2C_FSL
553 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
554 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
559 #undef CONFIG_ID_EEPROM
561 #define CONFIG_RTC_PT7C4338
562 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
563 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
565 /* enable read and write access to EEPROM */
566 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
567 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
568 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
570 #if defined(CONFIG_PCI)
573 * Memory space is mapped 1-1, but I/O space must start from 0.
576 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
577 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
578 #ifdef CONFIG_PHYS_64BIT
579 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
581 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
583 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
584 #ifdef CONFIG_PHYS_64BIT
585 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
587 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
590 /* controller 1, Slot 2, tgtid 1, Base address a000 */
591 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
592 #ifdef CONFIG_PHYS_64BIT
593 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
595 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
597 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
598 #ifdef CONFIG_PHYS_64BIT
599 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
601 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
604 #if !defined(CONFIG_DM_PCI)
605 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
606 #define CONFIG_PCI_INDIRECT_BRIDGE
607 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
608 #ifdef CONFIG_PHYS_64BIT
609 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
611 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
613 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
614 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
615 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
617 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
618 #ifdef CONFIG_PHYS_64BIT
619 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
621 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
623 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
624 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
625 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
628 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
629 #endif /* CONFIG_PCI */
631 #if defined(CONFIG_TSEC_ENET)
633 #define CONFIG_TSEC1_NAME "eTSEC1"
635 #define CONFIG_TSEC2_NAME "eTSEC2"
637 #define CONFIG_TSEC3_NAME "eTSEC3"
639 #define TSEC1_PHY_ADDR 2
640 #define TSEC2_PHY_ADDR 0
641 #define TSEC3_PHY_ADDR 1
643 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
644 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
645 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
647 #define TSEC1_PHYIDX 0
648 #define TSEC2_PHYIDX 0
649 #define TSEC3_PHYIDX 0
651 #define CONFIG_ETHPRIME "eTSEC1"
653 #define CONFIG_HAS_ETH0
654 #define CONFIG_HAS_ETH1
655 #define CONFIG_HAS_ETH2
656 #endif /* CONFIG_TSEC_ENET */
659 /* QE microcode/firmware address */
660 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
661 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
662 #endif /* CONFIG_QE */
664 #ifdef CONFIG_TARGET_P1025RDB
666 * QE UEC ethernet configuration
668 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
670 #undef CONFIG_UEC_ETH
671 #define CONFIG_PHY_MODE_NEED_CHANGE
673 #define CONFIG_UEC_ETH1 /* ETH1 */
674 #define CONFIG_HAS_ETH0
676 #ifdef CONFIG_UEC_ETH1
677 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
678 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
679 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
680 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
681 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
682 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
683 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
684 #endif /* CONFIG_UEC_ETH1 */
686 #define CONFIG_UEC_ETH5 /* ETH5 */
687 #define CONFIG_HAS_ETH1
689 #ifdef CONFIG_UEC_ETH5
690 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
691 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
692 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
693 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
694 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
695 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
696 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
697 #endif /* CONFIG_UEC_ETH5 */
698 #endif /* CONFIG_TARGET_P1025RDB */
703 #if defined(CONFIG_SDCARD)
704 #define CONFIG_FSL_FIXED_MMC_LOCATION
705 #define CONFIG_SYS_MMC_ENV_DEV 0
706 #elif defined(CONFIG_MTD_RAW_NAND)
707 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
708 #ifdef CONFIG_TPL_BUILD
709 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
711 #elif defined(CONFIG_SYS_RAMBOOT)
712 #define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
715 #define CONFIG_LOADS_ECHO /* echo on for serial download */
716 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
721 #define CONFIG_HAS_FSL_DR_USB
723 #if defined(CONFIG_HAS_FSL_DR_USB)
724 #ifdef CONFIG_USB_EHCI_HCD
725 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
726 #define CONFIG_USB_EHCI_FSL
730 #if defined(CONFIG_TARGET_P1020RDB_PD)
731 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
735 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
738 #undef CONFIG_WATCHDOG /* watchdog disabled */
741 * Miscellaneous configurable options
743 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
746 * For booting Linux, the board info and command line data
747 * have to be in the first 64 MB of memory, since this is
748 * the maximum mapped by the Linux kernel during initialization.
750 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
751 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
753 #if defined(CONFIG_CMD_KGDB)
754 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
758 * Environment Configuration
760 #define CONFIG_HOSTNAME "unknown"
761 #define CONFIG_ROOTPATH "/opt/nfsroot"
762 #define CONFIG_BOOTFILE "uImage"
763 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
765 /* default location for tftp and bootm */
766 #define CONFIG_LOADADDR 1000000
769 #define __NOR_RST_CMD \
770 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
771 i2c mw 18 3 __SW_BOOT_MASK 1; reset
774 #define __SPI_RST_CMD \
775 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
776 i2c mw 18 3 __SW_BOOT_MASK 1; reset
779 #define __SD_RST_CMD \
780 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
781 i2c mw 18 3 __SW_BOOT_MASK 1; reset
783 #ifdef __SW_BOOT_NAND
784 #define __NAND_RST_CMD \
785 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
786 i2c mw 18 3 __SW_BOOT_MASK 1; reset
788 #ifdef __SW_BOOT_PCIE
789 #define __PCIE_RST_CMD \
790 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
791 i2c mw 18 3 __SW_BOOT_MASK 1; reset
794 #define CONFIG_EXTRA_ENV_SETTINGS \
796 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
797 "loadaddr=1000000\0" \
798 "bootfile=uImage\0" \
799 "tftpflash=tftpboot $loadaddr $uboot; " \
800 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
801 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
802 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
803 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
804 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
805 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
806 "consoledev=ttyS0\0" \
807 "ramdiskaddr=2000000\0" \
808 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
809 "fdtaddr=1e00000\0" \
811 "jffs2nor=mtdblock3\0" \
812 "norbootaddr=ef080000\0" \
813 "norfdtaddr=ef040000\0" \
814 "jffs2nand=mtdblock9\0" \
815 "nandbootaddr=100000\0" \
816 "nandfdtaddr=80000\0" \
817 "ramdisk_size=120000\0" \
818 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
819 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
820 __stringify(__NOR_RST_CMD)"\0" \
821 __stringify(__SPI_RST_CMD)"\0" \
822 __stringify(__SD_RST_CMD)"\0" \
823 __stringify(__NAND_RST_CMD)"\0" \
824 __stringify(__PCIE_RST_CMD)"\0"
826 #define CONFIG_NFSBOOTCOMMAND \
827 "setenv bootargs root=/dev/nfs rw " \
828 "nfsroot=$serverip:$rootpath " \
829 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
830 "console=$consoledev,$baudrate $othbootargs;" \
831 "tftp $loadaddr $bootfile;" \
832 "tftp $fdtaddr $fdtfile;" \
833 "bootm $loadaddr - $fdtaddr"
835 #define CONFIG_HDBOOT \
836 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
837 "console=$consoledev,$baudrate $othbootargs;" \
839 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
840 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
841 "bootm $loadaddr - $fdtaddr"
843 #define CONFIG_USB_FAT_BOOT \
844 "setenv bootargs root=/dev/ram rw " \
845 "console=$consoledev,$baudrate $othbootargs " \
846 "ramdisk_size=$ramdisk_size;" \
848 "fatload usb 0:2 $loadaddr $bootfile;" \
849 "fatload usb 0:2 $fdtaddr $fdtfile;" \
850 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
851 "bootm $loadaddr $ramdiskaddr $fdtaddr"
853 #define CONFIG_USB_EXT2_BOOT \
854 "setenv bootargs root=/dev/ram rw " \
855 "console=$consoledev,$baudrate $othbootargs " \
856 "ramdisk_size=$ramdisk_size;" \
858 "ext2load usb 0:4 $loadaddr $bootfile;" \
859 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
860 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
861 "bootm $loadaddr $ramdiskaddr $fdtaddr"
863 #define CONFIG_NORBOOT \
864 "setenv bootargs root=/dev/$jffs2nor rw " \
865 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
866 "bootm $norbootaddr - $norfdtaddr"
868 #define CONFIG_RAMBOOTCOMMAND \
869 "setenv bootargs root=/dev/ram rw " \
870 "console=$consoledev,$baudrate $othbootargs " \
871 "ramdisk_size=$ramdisk_size;" \
872 "tftp $ramdiskaddr $ramdiskfile;" \
873 "tftp $loadaddr $bootfile;" \
874 "tftp $fdtaddr $fdtfile;" \
875 "bootm $loadaddr $ramdiskaddr $fdtaddr"
877 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
879 #endif /* __CONFIG_H */