1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
7 * QorIQ RDB boards configuration file
12 #if defined(CONFIG_TARGET_P1020MBG)
13 #define CONFIG_BOARDNAME "P1020MBG-PC"
14 #define CONFIG_VSC7385_ENET
16 #define __SW_BOOT_MASK 0x03
17 #define __SW_BOOT_NOR 0xe4
18 #define __SW_BOOT_SD 0x54
19 #define CONFIG_SYS_L2_SIZE (256 << 10)
22 #if defined(CONFIG_TARGET_P1020UTM)
23 #define CONFIG_BOARDNAME "P1020UTM-PC"
24 #define __SW_BOOT_MASK 0x03
25 #define __SW_BOOT_NOR 0xe0
26 #define __SW_BOOT_SD 0x50
27 #define CONFIG_SYS_L2_SIZE (256 << 10)
30 #if defined(CONFIG_TARGET_P1020RDB_PC)
31 #define CONFIG_BOARDNAME "P1020RDB-PC"
32 #define CONFIG_NAND_FSL_ELBC
33 #define CONFIG_VSC7385_ENET
35 #define __SW_BOOT_MASK 0x03
36 #define __SW_BOOT_NOR 0x5c
37 #define __SW_BOOT_SPI 0x1c
38 #define __SW_BOOT_SD 0x9c
39 #define __SW_BOOT_NAND 0xec
40 #define __SW_BOOT_PCIE 0x6c
41 #define CONFIG_SYS_L2_SIZE (256 << 10)
45 * P1020RDB-PD board has user selectable switches for evaluating different
46 * frequency and boot options for the P1020 device. The table that
47 * follow describe the available options. The front six binary number was in
48 * accordance with SW3[1:6].
49 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
50 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
51 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
52 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
53 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
54 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
55 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
57 #if defined(CONFIG_TARGET_P1020RDB_PD)
58 #define CONFIG_BOARDNAME "P1020RDB-PD"
59 #define CONFIG_NAND_FSL_ELBC
60 #define CONFIG_VSC7385_ENET
62 #define __SW_BOOT_MASK 0x03
63 #define __SW_BOOT_NOR 0x64
64 #define __SW_BOOT_SPI 0x34
65 #define __SW_BOOT_SD 0x24
66 #define __SW_BOOT_NAND 0x44
67 #define __SW_BOOT_PCIE 0x74
68 #define CONFIG_SYS_L2_SIZE (256 << 10)
70 * Dynamic MTD Partition support with mtdparts
72 #define CONFIG_MTD_DEVICE
73 #define CONFIG_MTD_PARTITIONS
74 #define CONFIG_FLASH_CFI_MTD
77 #if defined(CONFIG_TARGET_P1021RDB)
78 #define CONFIG_BOARDNAME "P1021RDB-PC"
79 #define CONFIG_NAND_FSL_ELBC
81 #define CONFIG_VSC7385_ENET
82 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
83 addresses in the LBC */
84 #define __SW_BOOT_MASK 0x03
85 #define __SW_BOOT_NOR 0x5c
86 #define __SW_BOOT_SPI 0x1c
87 #define __SW_BOOT_SD 0x9c
88 #define __SW_BOOT_NAND 0xec
89 #define __SW_BOOT_PCIE 0x6c
90 #define CONFIG_SYS_L2_SIZE (256 << 10)
92 * Dynamic MTD Partition support with mtdparts
94 #define CONFIG_MTD_DEVICE
95 #define CONFIG_MTD_PARTITIONS
96 #define CONFIG_FLASH_CFI_MTD
99 #if defined(CONFIG_TARGET_P1024RDB)
100 #define CONFIG_BOARDNAME "P1024RDB"
101 #define CONFIG_NAND_FSL_ELBC
103 #define __SW_BOOT_MASK 0xf3
104 #define __SW_BOOT_NOR 0x00
105 #define __SW_BOOT_SPI 0x08
106 #define __SW_BOOT_SD 0x04
107 #define __SW_BOOT_NAND 0x0c
108 #define CONFIG_SYS_L2_SIZE (256 << 10)
111 #if defined(CONFIG_TARGET_P1025RDB)
112 #define CONFIG_BOARDNAME "P1025RDB"
113 #define CONFIG_NAND_FSL_ELBC
117 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
118 addresses in the LBC */
119 #define __SW_BOOT_MASK 0xf3
120 #define __SW_BOOT_NOR 0x00
121 #define __SW_BOOT_SPI 0x08
122 #define __SW_BOOT_SD 0x04
123 #define __SW_BOOT_NAND 0x0c
124 #define CONFIG_SYS_L2_SIZE (256 << 10)
127 #if defined(CONFIG_TARGET_P2020RDB)
128 #define CONFIG_BOARDNAME "P2020RDB-PC"
129 #define CONFIG_NAND_FSL_ELBC
130 #define CONFIG_VSC7385_ENET
131 #define __SW_BOOT_MASK 0x03
132 #define __SW_BOOT_NOR 0xc8
133 #define __SW_BOOT_SPI 0x28
134 #define __SW_BOOT_SD 0x68 /* or 0x18 */
135 #define __SW_BOOT_NAND 0xe8
136 #define __SW_BOOT_PCIE 0xa8
137 #define CONFIG_SYS_L2_SIZE (512 << 10)
139 * Dynamic MTD Partition support with mtdparts
141 #define CONFIG_MTD_DEVICE
142 #define CONFIG_MTD_PARTITIONS
143 #define CONFIG_FLASH_CFI_MTD
147 #define CONFIG_SPL_FLUSH_IMAGE
148 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
149 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
150 #define CONFIG_SPL_PAD_TO 0x20000
151 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
152 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
153 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
154 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
155 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
156 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
157 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
158 #define CONFIG_SPL_MMC_BOOT
159 #ifdef CONFIG_SPL_BUILD
160 #define CONFIG_SPL_COMMON_INIT_DDR
164 #ifdef CONFIG_SPIFLASH
165 #define CONFIG_SPL_SPI_FLASH_MINIMAL
166 #define CONFIG_SPL_FLUSH_IMAGE
167 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
168 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
169 #define CONFIG_SPL_PAD_TO 0x20000
170 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
171 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
172 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
173 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
174 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
175 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
176 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
177 #define CONFIG_SPL_SPI_BOOT
178 #ifdef CONFIG_SPL_BUILD
179 #define CONFIG_SPL_COMMON_INIT_DDR
184 #ifdef CONFIG_TPL_BUILD
185 #define CONFIG_SPL_NAND_BOOT
186 #define CONFIG_SPL_FLUSH_IMAGE
187 #define CONFIG_SPL_NAND_INIT
188 #define CONFIG_SPL_COMMON_INIT_DDR
189 #define CONFIG_SPL_MAX_SIZE (128 << 10)
190 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
191 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
192 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
193 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
194 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
195 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
196 #elif defined(CONFIG_SPL_BUILD)
197 #define CONFIG_SPL_INIT_MINIMAL
198 #define CONFIG_SPL_FLUSH_IMAGE
199 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
200 #define CONFIG_SPL_TEXT_BASE 0xff800000
201 #define CONFIG_SPL_MAX_SIZE 4096
202 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
203 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
204 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
205 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
206 #endif /* not CONFIG_TPL_BUILD */
208 #define CONFIG_SPL_PAD_TO 0x20000
209 #define CONFIG_TPL_PAD_TO 0x20000
210 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
211 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
214 #ifndef CONFIG_RESET_VECTOR_ADDRESS
215 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
218 #ifndef CONFIG_SYS_MONITOR_BASE
219 #ifdef CONFIG_SPL_BUILD
220 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
222 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
226 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
227 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
228 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
229 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
230 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
231 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
233 #define CONFIG_ENV_OVERWRITE
235 #define CONFIG_SYS_SATA_MAX_DEVICE 2
238 #if defined(CONFIG_TARGET_P2020RDB)
239 #define CONFIG_SYS_CLK_FREQ 100000000
241 #define CONFIG_SYS_CLK_FREQ 66666666
243 #define CONFIG_DDR_CLK_FREQ 66666666
245 #define CONFIG_HWCONFIG
247 * These can be toggled for performance analysis, otherwise use default.
249 #define CONFIG_L2_CACHE
252 #define CONFIG_ENABLE_36BIT_PHYS
254 #ifdef CONFIG_PHYS_64BIT
255 #define CONFIG_ADDR_MAP 1
256 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
259 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
260 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
262 #define CONFIG_SYS_CCSRBAR 0xffe00000
263 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
265 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
267 #ifdef CONFIG_SPL_BUILD
268 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
272 #define CONFIG_SYS_DDR_RAW_TIMING
273 #define CONFIG_DDR_SPD
274 #define CONFIG_SYS_SPD_BUS_NUM 1
275 #define SPD_EEPROM_ADDRESS 0x52
276 #undef CONFIG_FSL_DDR_INTERACTIVE
278 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
279 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
280 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
282 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
283 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
285 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
286 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
287 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
289 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
291 /* Default settings for DDR3 */
292 #ifndef CONFIG_TARGET_P2020RDB
293 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
294 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
295 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
296 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
297 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
298 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
300 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
301 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
302 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
303 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
305 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
306 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
307 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
308 #define CONFIG_SYS_DDR_RCW_1 0x00000000
309 #define CONFIG_SYS_DDR_RCW_2 0x00000000
310 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
311 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
312 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
313 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
315 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
316 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
317 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
318 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
319 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
320 #define CONFIG_SYS_DDR_MODE_1 0x40461520
321 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
322 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
325 #undef CONFIG_CLOCKS_IN_MHZ
330 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
331 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
332 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
333 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
335 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
336 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
337 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
338 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
339 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
340 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
341 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
345 * Local Bus Definitions
347 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
348 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
349 #define CONFIG_SYS_FLASH_BASE 0xec000000
350 #elif defined(CONFIG_TARGET_P1020UTM)
351 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
352 #define CONFIG_SYS_FLASH_BASE 0xee000000
354 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
355 #define CONFIG_SYS_FLASH_BASE 0xef000000
358 #ifdef CONFIG_PHYS_64BIT
359 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
361 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
364 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
367 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
369 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
370 #define CONFIG_SYS_FLASH_QUIET_TEST
371 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
373 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
375 #undef CONFIG_SYS_FLASH_CHECKSUM
376 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
377 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
379 #define CONFIG_FLASH_CFI_DRIVER
380 #define CONFIG_SYS_FLASH_CFI
381 #define CONFIG_SYS_FLASH_EMPTY_INFO
382 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
385 #ifdef CONFIG_NAND_FSL_ELBC
386 #define CONFIG_SYS_NAND_BASE 0xff800000
387 #ifdef CONFIG_PHYS_64BIT
388 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
390 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
393 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
394 #define CONFIG_SYS_MAX_NAND_DEVICE 1
395 #if defined(CONFIG_TARGET_P1020RDB_PD)
396 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
398 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
401 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
402 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
403 | BR_PS_8 /* Port Size = 8 bit */ \
404 | BR_MS_FCM /* MSEL = FCM */ \
406 #if defined(CONFIG_TARGET_P1020RDB_PD)
407 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
408 | OR_FCM_PGS /* Large Page*/ \
416 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
424 #endif /* CONFIG_NAND_FSL_ELBC */
426 #define CONFIG_SYS_INIT_RAM_LOCK
427 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
428 #ifdef CONFIG_PHYS_64BIT
429 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
430 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
431 /* The assembler doesn't like typecast */
432 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
433 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
434 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
436 /* Initial L1 address */
437 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
438 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
439 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
441 /* Size of used area in RAM */
442 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
444 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
445 GENERATED_GBL_DATA_SIZE)
446 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
448 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
449 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
451 #define CONFIG_SYS_CPLD_BASE 0xffa00000
452 #ifdef CONFIG_PHYS_64BIT
453 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
455 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
457 /* CPLD config size: 1Mb */
458 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
460 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
462 #define CONFIG_SYS_PMC_BASE 0xff980000
463 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
464 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
466 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
467 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
471 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
472 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
473 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
474 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
476 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
477 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
478 #ifdef CONFIG_NAND_FSL_ELBC
479 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
480 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
483 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
484 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
487 #ifdef CONFIG_VSC7385_ENET
488 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
490 #ifdef CONFIG_PHYS_64BIT
491 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
493 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
496 #define CONFIG_SYS_VSC7385_BR_PRELIM \
497 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
498 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
499 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
500 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
502 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
503 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
505 /* The size of the VSC7385 firmware image */
506 #define CONFIG_VSC7385_IMAGE_SIZE 8192
510 * Config the L2 Cache as L2 SRAM
512 #if defined(CONFIG_SPL_BUILD)
513 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
514 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
515 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
516 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
517 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
518 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
519 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
520 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
521 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
522 #if defined(CONFIG_TARGET_P2020RDB)
523 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
525 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
527 #elif defined(CONFIG_NAND)
528 #ifdef CONFIG_TPL_BUILD
529 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
530 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
531 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
532 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
533 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
534 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
535 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
536 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
538 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
539 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
540 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
541 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
542 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
543 #endif /* CONFIG_TPL_BUILD */
547 /* Serial Port - controlled on board with jumper J8
551 #undef CONFIG_SERIAL_SOFTWARE_FIFO
552 #define CONFIG_SYS_NS16550_SERIAL
553 #define CONFIG_SYS_NS16550_REG_SIZE 1
554 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
555 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
556 #define CONFIG_NS16550_MIN_FUNCTIONS
559 #define CONFIG_SYS_BAUDRATE_TABLE \
560 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
562 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
563 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
566 #define CONFIG_SYS_I2C
567 #define CONFIG_SYS_I2C_FSL
568 #define CONFIG_SYS_FSL_I2C_SPEED 400000
569 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
570 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
571 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
572 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
573 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
574 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
575 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
576 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
581 #undef CONFIG_ID_EEPROM
583 #define CONFIG_RTC_PT7C4338
584 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
585 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
587 /* enable read and write access to EEPROM */
588 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
589 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
590 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
593 * eSPI - Enhanced SPI
595 #define CONFIG_HARD_SPI
597 #if defined(CONFIG_SPI_FLASH)
598 #define CONFIG_SF_DEFAULT_SPEED 10000000
599 #define CONFIG_SF_DEFAULT_MODE 0
602 #if defined(CONFIG_PCI)
605 * Memory space is mapped 1-1, but I/O space must start from 0.
608 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
609 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
610 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
611 #ifdef CONFIG_PHYS_64BIT
612 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
613 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
615 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
616 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
618 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
619 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
620 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
621 #ifdef CONFIG_PHYS_64BIT
622 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
624 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
626 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
628 /* controller 1, Slot 2, tgtid 1, Base address a000 */
629 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
630 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
631 #ifdef CONFIG_PHYS_64BIT
632 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
633 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
635 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
636 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
638 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
639 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
640 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
641 #ifdef CONFIG_PHYS_64BIT
642 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
644 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
646 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
648 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
649 #endif /* CONFIG_PCI */
651 #if defined(CONFIG_TSEC_ENET)
652 #define CONFIG_MII /* MII PHY management */
654 #define CONFIG_TSEC1_NAME "eTSEC1"
656 #define CONFIG_TSEC2_NAME "eTSEC2"
658 #define CONFIG_TSEC3_NAME "eTSEC3"
660 #define TSEC1_PHY_ADDR 2
661 #define TSEC2_PHY_ADDR 0
662 #define TSEC3_PHY_ADDR 1
664 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
665 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
666 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
668 #define TSEC1_PHYIDX 0
669 #define TSEC2_PHYIDX 0
670 #define TSEC3_PHYIDX 0
672 #define CONFIG_ETHPRIME "eTSEC1"
674 #define CONFIG_HAS_ETH0
675 #define CONFIG_HAS_ETH1
676 #define CONFIG_HAS_ETH2
677 #endif /* CONFIG_TSEC_ENET */
680 /* QE microcode/firmware address */
681 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
682 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
683 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
684 #endif /* CONFIG_QE */
686 #ifdef CONFIG_TARGET_P1025RDB
688 * QE UEC ethernet configuration
690 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
692 #undef CONFIG_UEC_ETH
693 #define CONFIG_PHY_MODE_NEED_CHANGE
695 #define CONFIG_UEC_ETH1 /* ETH1 */
696 #define CONFIG_HAS_ETH0
698 #ifdef CONFIG_UEC_ETH1
699 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
700 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
701 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
702 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
703 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
704 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
705 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
706 #endif /* CONFIG_UEC_ETH1 */
708 #define CONFIG_UEC_ETH5 /* ETH5 */
709 #define CONFIG_HAS_ETH1
711 #ifdef CONFIG_UEC_ETH5
712 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
713 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
714 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
715 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
716 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
717 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
718 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
719 #endif /* CONFIG_UEC_ETH5 */
720 #endif /* CONFIG_TARGET_P1025RDB */
725 #ifdef CONFIG_SPIFLASH
726 #define CONFIG_ENV_SPI_BUS 0
727 #define CONFIG_ENV_SPI_CS 0
728 #define CONFIG_ENV_SPI_MAX_HZ 10000000
729 #define CONFIG_ENV_SPI_MODE 0
730 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
731 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
732 #define CONFIG_ENV_SECT_SIZE 0x10000
733 #elif defined(CONFIG_SDCARD)
734 #define CONFIG_FSL_FIXED_MMC_LOCATION
735 #define CONFIG_ENV_SIZE 0x2000
736 #define CONFIG_SYS_MMC_ENV_DEV 0
737 #elif defined(CONFIG_NAND)
738 #ifdef CONFIG_TPL_BUILD
739 #define CONFIG_ENV_SIZE 0x2000
740 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
742 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
744 #define CONFIG_ENV_OFFSET (1024 * 1024)
745 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
746 #elif defined(CONFIG_SYS_RAMBOOT)
747 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
748 #define CONFIG_ENV_SIZE 0x2000
750 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
751 #define CONFIG_ENV_SIZE 0x2000
752 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
755 #define CONFIG_LOADS_ECHO /* echo on for serial download */
756 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
761 #define CONFIG_HAS_FSL_DR_USB
763 #if defined(CONFIG_HAS_FSL_DR_USB)
764 #ifdef CONFIG_USB_EHCI_HCD
765 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
766 #define CONFIG_USB_EHCI_FSL
767 #define CONFIG_EHCI_DESC_BIG_ENDIAN
771 #if defined(CONFIG_TARGET_P1020RDB_PD)
772 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
776 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
779 #undef CONFIG_WATCHDOG /* watchdog disabled */
782 * Miscellaneous configurable options
784 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
787 * For booting Linux, the board info and command line data
788 * have to be in the first 64 MB of memory, since this is
789 * the maximum mapped by the Linux kernel during initialization.
791 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
792 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
794 #if defined(CONFIG_CMD_KGDB)
795 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
799 * Environment Configuration
801 #define CONFIG_HOSTNAME "unknown"
802 #define CONFIG_ROOTPATH "/opt/nfsroot"
803 #define CONFIG_BOOTFILE "uImage"
804 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
806 /* default location for tftp and bootm */
807 #define CONFIG_LOADADDR 1000000
810 #define __NOR_RST_CMD \
811 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
812 i2c mw 18 3 __SW_BOOT_MASK 1; reset
815 #define __SPI_RST_CMD \
816 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
817 i2c mw 18 3 __SW_BOOT_MASK 1; reset
820 #define __SD_RST_CMD \
821 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
822 i2c mw 18 3 __SW_BOOT_MASK 1; reset
824 #ifdef __SW_BOOT_NAND
825 #define __NAND_RST_CMD \
826 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
827 i2c mw 18 3 __SW_BOOT_MASK 1; reset
829 #ifdef __SW_BOOT_PCIE
830 #define __PCIE_RST_CMD \
831 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
832 i2c mw 18 3 __SW_BOOT_MASK 1; reset
835 #define CONFIG_EXTRA_ENV_SETTINGS \
837 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
838 "loadaddr=1000000\0" \
839 "bootfile=uImage\0" \
840 "tftpflash=tftpboot $loadaddr $uboot; " \
841 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
842 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
843 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
844 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
845 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
846 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
847 "consoledev=ttyS0\0" \
848 "ramdiskaddr=2000000\0" \
849 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
850 "fdtaddr=1e00000\0" \
852 "jffs2nor=mtdblock3\0" \
853 "norbootaddr=ef080000\0" \
854 "norfdtaddr=ef040000\0" \
855 "jffs2nand=mtdblock9\0" \
856 "nandbootaddr=100000\0" \
857 "nandfdtaddr=80000\0" \
858 "ramdisk_size=120000\0" \
859 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
860 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
861 __stringify(__NOR_RST_CMD)"\0" \
862 __stringify(__SPI_RST_CMD)"\0" \
863 __stringify(__SD_RST_CMD)"\0" \
864 __stringify(__NAND_RST_CMD)"\0" \
865 __stringify(__PCIE_RST_CMD)"\0"
867 #define CONFIG_NFSBOOTCOMMAND \
868 "setenv bootargs root=/dev/nfs rw " \
869 "nfsroot=$serverip:$rootpath " \
870 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
871 "console=$consoledev,$baudrate $othbootargs;" \
872 "tftp $loadaddr $bootfile;" \
873 "tftp $fdtaddr $fdtfile;" \
874 "bootm $loadaddr - $fdtaddr"
876 #define CONFIG_HDBOOT \
877 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
878 "console=$consoledev,$baudrate $othbootargs;" \
880 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
881 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
882 "bootm $loadaddr - $fdtaddr"
884 #define CONFIG_USB_FAT_BOOT \
885 "setenv bootargs root=/dev/ram rw " \
886 "console=$consoledev,$baudrate $othbootargs " \
887 "ramdisk_size=$ramdisk_size;" \
889 "fatload usb 0:2 $loadaddr $bootfile;" \
890 "fatload usb 0:2 $fdtaddr $fdtfile;" \
891 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
892 "bootm $loadaddr $ramdiskaddr $fdtaddr"
894 #define CONFIG_USB_EXT2_BOOT \
895 "setenv bootargs root=/dev/ram rw " \
896 "console=$consoledev,$baudrate $othbootargs " \
897 "ramdisk_size=$ramdisk_size;" \
899 "ext2load usb 0:4 $loadaddr $bootfile;" \
900 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
901 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
902 "bootm $loadaddr $ramdiskaddr $fdtaddr"
904 #define CONFIG_NORBOOT \
905 "setenv bootargs root=/dev/$jffs2nor rw " \
906 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
907 "bootm $norbootaddr - $norfdtaddr"
909 #define CONFIG_RAMBOOTCOMMAND \
910 "setenv bootargs root=/dev/ram rw " \
911 "console=$consoledev,$baudrate $othbootargs " \
912 "ramdisk_size=$ramdisk_size;" \
913 "tftp $ramdiskaddr $ramdiskfile;" \
914 "tftp $loadaddr $bootfile;" \
915 "tftp $fdtaddr $fdtfile;" \
916 "bootm $loadaddr $ramdiskaddr $fdtaddr"
918 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
920 #endif /* __CONFIG_H */