1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * QorIQ RDB boards configuration file
13 #include <linux/stringify.h>
15 #if defined(CONFIG_TARGET_P1020MBG)
16 #define CONFIG_BOARDNAME "P1020MBG-PC"
17 #define CONFIG_VSC7385_ENET
19 #define __SW_BOOT_MASK 0x03
20 #define __SW_BOOT_NOR 0xe4
21 #define __SW_BOOT_SD 0x54
22 #define CONFIG_SYS_L2_SIZE (256 << 10)
25 #if defined(CONFIG_TARGET_P1020RDB_PC)
26 #define CONFIG_BOARDNAME "P1020RDB-PC"
27 #define CONFIG_NAND_FSL_ELBC
28 #define CONFIG_VSC7385_ENET
30 #define __SW_BOOT_MASK 0x03
31 #define __SW_BOOT_NOR 0x5c
32 #define __SW_BOOT_SPI 0x1c
33 #define __SW_BOOT_SD 0x9c
34 #define __SW_BOOT_NAND 0xec
35 #define __SW_BOOT_PCIE 0x6c
36 #define CONFIG_SYS_L2_SIZE (256 << 10)
40 * P1020RDB-PD board has user selectable switches for evaluating different
41 * frequency and boot options for the P1020 device. The table that
42 * follow describe the available options. The front six binary number was in
43 * accordance with SW3[1:6].
44 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
45 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
46 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
47 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
48 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
49 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
50 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
52 #if defined(CONFIG_TARGET_P1020RDB_PD)
53 #define CONFIG_BOARDNAME "P1020RDB-PD"
54 #define CONFIG_NAND_FSL_ELBC
55 #define CONFIG_VSC7385_ENET
57 #define __SW_BOOT_MASK 0x03
58 #define __SW_BOOT_NOR 0x64
59 #define __SW_BOOT_SPI 0x34
60 #define __SW_BOOT_SD 0x24
61 #define __SW_BOOT_NAND 0x44
62 #define __SW_BOOT_PCIE 0x74
63 #define CONFIG_SYS_L2_SIZE (256 << 10)
65 * Dynamic MTD Partition support with mtdparts
69 #if defined(CONFIG_TARGET_P1021RDB)
70 #define CONFIG_BOARDNAME "P1021RDB-PC"
71 #define CONFIG_NAND_FSL_ELBC
72 #define CONFIG_VSC7385_ENET
73 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
74 addresses in the LBC */
75 #define __SW_BOOT_MASK 0x03
76 #define __SW_BOOT_NOR 0x5c
77 #define __SW_BOOT_SPI 0x1c
78 #define __SW_BOOT_SD 0x9c
79 #define __SW_BOOT_NAND 0xec
80 #define __SW_BOOT_PCIE 0x6c
81 #define CONFIG_SYS_L2_SIZE (256 << 10)
83 * Dynamic MTD Partition support with mtdparts
87 #if defined(CONFIG_TARGET_P1024RDB)
88 #define CONFIG_BOARDNAME "P1024RDB"
89 #define CONFIG_NAND_FSL_ELBC
91 #define __SW_BOOT_MASK 0xf3
92 #define __SW_BOOT_NOR 0x00
93 #define __SW_BOOT_SPI 0x08
94 #define __SW_BOOT_SD 0x04
95 #define __SW_BOOT_NAND 0x0c
96 #define CONFIG_SYS_L2_SIZE (256 << 10)
99 #if defined(CONFIG_TARGET_P2020RDB)
100 #define CONFIG_BOARDNAME "P2020RDB-PC"
101 #define CONFIG_NAND_FSL_ELBC
102 #define CONFIG_VSC7385_ENET
103 #define __SW_BOOT_MASK 0x03
104 #define __SW_BOOT_NOR 0xc8
105 #define __SW_BOOT_SPI 0x28
106 #define __SW_BOOT_SD 0x68 /* or 0x18 */
107 #define __SW_BOOT_NAND 0xe8
108 #define __SW_BOOT_PCIE 0xa8
109 #define CONFIG_SYS_L2_SIZE (512 << 10)
111 * Dynamic MTD Partition support with mtdparts
116 #define CONFIG_SPL_FLUSH_IMAGE
117 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
118 #define CONFIG_SPL_PAD_TO 0x20000
119 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
120 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
121 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
122 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
123 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
124 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
125 #ifdef CONFIG_SPL_BUILD
126 #define CONFIG_SPL_COMMON_INIT_DDR
130 #ifdef CONFIG_SPIFLASH
131 #define CONFIG_SPL_SPI_FLASH_MINIMAL
132 #define CONFIG_SPL_FLUSH_IMAGE
133 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
134 #define CONFIG_SPL_PAD_TO 0x20000
135 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
136 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
137 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
138 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
139 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
140 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
141 #ifdef CONFIG_SPL_BUILD
142 #define CONFIG_SPL_COMMON_INIT_DDR
146 #ifdef CONFIG_MTD_RAW_NAND
147 #ifdef CONFIG_TPL_BUILD
148 #define CONFIG_SPL_FLUSH_IMAGE
149 #define CONFIG_SPL_NAND_INIT
150 #define CONFIG_SPL_COMMON_INIT_DDR
151 #define CONFIG_SPL_MAX_SIZE (128 << 10)
152 #define CONFIG_TPL_TEXT_BASE 0xf8f81000
153 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
154 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
155 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
156 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
157 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
158 #elif defined(CONFIG_SPL_BUILD)
159 #define CONFIG_SPL_INIT_MINIMAL
160 #define CONFIG_SPL_FLUSH_IMAGE
161 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
162 #define CONFIG_SPL_MAX_SIZE 4096
163 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
164 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
165 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
166 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
167 #endif /* not CONFIG_TPL_BUILD */
169 #define CONFIG_SPL_PAD_TO 0x20000
170 #define CONFIG_TPL_PAD_TO 0x20000
171 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
174 #ifndef CONFIG_RESET_VECTOR_ADDRESS
175 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
178 #ifndef CONFIG_SYS_MONITOR_BASE
179 #ifdef CONFIG_TPL_BUILD
180 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
181 #elif defined(CONFIG_SPL_BUILD)
182 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
184 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
188 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
189 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
190 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
192 #define CONFIG_SYS_SATA_MAX_DEVICE 2
195 #if defined(CONFIG_TARGET_P2020RDB)
196 #define CONFIG_SYS_CLK_FREQ 100000000
198 #define CONFIG_SYS_CLK_FREQ 66666666
200 #define CONFIG_DDR_CLK_FREQ 66666666
202 #define CONFIG_HWCONFIG
204 * These can be toggled for performance analysis, otherwise use default.
206 #define CONFIG_L2_CACHE
209 #define CONFIG_ENABLE_36BIT_PHYS
211 #define CONFIG_SYS_CCSRBAR 0xffe00000
212 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
214 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
216 #ifdef CONFIG_SPL_BUILD
217 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
221 #define CONFIG_SYS_DDR_RAW_TIMING
222 #define CONFIG_DDR_SPD
223 #define CONFIG_SYS_SPD_BUS_NUM 1
224 #define SPD_EEPROM_ADDRESS 0x52
226 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
227 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
228 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
230 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
231 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
233 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
234 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
235 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
237 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
239 /* Default settings for DDR3 */
240 #ifndef CONFIG_TARGET_P2020RDB
241 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
242 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
243 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
244 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
245 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
246 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
248 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
249 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
250 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
251 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
253 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
254 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
255 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
256 #define CONFIG_SYS_DDR_RCW_1 0x00000000
257 #define CONFIG_SYS_DDR_RCW_2 0x00000000
258 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
259 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
260 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
261 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
263 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
264 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
265 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
266 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
267 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
268 #define CONFIG_SYS_DDR_MODE_1 0x40461520
269 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
270 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
276 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
277 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
278 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
279 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
281 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
282 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
283 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
284 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
285 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
286 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
287 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
291 * Local Bus Definitions
293 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
294 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
295 #define CONFIG_SYS_FLASH_BASE 0xec000000
297 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
298 #define CONFIG_SYS_FLASH_BASE 0xef000000
301 #ifdef CONFIG_PHYS_64BIT
302 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
304 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
307 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
310 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
312 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
313 #define CONFIG_SYS_FLASH_QUIET_TEST
314 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
316 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
318 #undef CONFIG_SYS_FLASH_CHECKSUM
319 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
320 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
322 #define CONFIG_SYS_FLASH_EMPTY_INFO
325 #ifdef CONFIG_NAND_FSL_ELBC
326 #define CONFIG_SYS_NAND_BASE 0xff800000
327 #ifdef CONFIG_PHYS_64BIT
328 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
330 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
333 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
334 #define CONFIG_SYS_MAX_NAND_DEVICE 1
335 #if defined(CONFIG_TARGET_P1020RDB_PD)
336 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
338 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
341 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
342 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
343 | BR_PS_8 /* Port Size = 8 bit */ \
344 | BR_MS_FCM /* MSEL = FCM */ \
346 #if defined(CONFIG_TARGET_P1020RDB_PD)
347 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
348 | OR_FCM_PGS /* Large Page*/ \
356 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
364 #endif /* CONFIG_NAND_FSL_ELBC */
366 #define CONFIG_SYS_INIT_RAM_LOCK
367 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
368 #ifdef CONFIG_PHYS_64BIT
369 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
370 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
371 /* The assembler doesn't like typecast */
372 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
373 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
374 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
376 /* Initial L1 address */
377 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
378 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
379 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
381 /* Size of used area in RAM */
382 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
384 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
385 GENERATED_GBL_DATA_SIZE)
386 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
388 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
389 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
391 #define CONFIG_SYS_CPLD_BASE 0xffa00000
392 #ifdef CONFIG_PHYS_64BIT
393 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
395 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
397 /* CPLD config size: 1Mb */
398 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
400 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
402 #define CONFIG_SYS_PMC_BASE 0xff980000
403 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
404 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
406 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
407 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
410 #ifdef CONFIG_MTD_RAW_NAND
411 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
412 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
413 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
414 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
416 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
417 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
418 #ifdef CONFIG_NAND_FSL_ELBC
419 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
420 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
423 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
424 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
427 #ifdef CONFIG_VSC7385_ENET
428 #define __VSCFW_ADDR "vscfw_addr=ef000000"
429 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
431 #ifdef CONFIG_PHYS_64BIT
432 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
434 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
437 #define CONFIG_SYS_VSC7385_BR_PRELIM \
438 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
439 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
440 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
441 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
443 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
444 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
446 /* The size of the VSC7385 firmware image */
447 #define CONFIG_VSC7385_IMAGE_SIZE 8192
451 * Config the L2 Cache as L2 SRAM
453 #if defined(CONFIG_SPL_BUILD)
454 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
455 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
456 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
457 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
458 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
459 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
460 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
461 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
462 #if defined(CONFIG_TARGET_P2020RDB)
463 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
465 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
467 #elif defined(CONFIG_MTD_RAW_NAND)
468 #ifdef CONFIG_TPL_BUILD
469 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
470 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
471 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
472 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
473 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
474 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
475 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
476 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
478 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
479 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
480 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
481 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
482 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
483 #endif /* CONFIG_TPL_BUILD */
487 /* Serial Port - controlled on board with jumper J8
491 #undef CONFIG_SERIAL_SOFTWARE_FIFO
492 #define CONFIG_SYS_NS16550_SERIAL
493 #define CONFIG_SYS_NS16550_REG_SIZE 1
494 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
495 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
496 #define CONFIG_NS16550_MIN_FUNCTIONS
499 #define CONFIG_SYS_BAUDRATE_TABLE \
500 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
502 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
503 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
506 #ifndef CONFIG_DM_I2C
507 #define CONFIG_SYS_I2C
508 #define CONFIG_SYS_FSL_I2C_SPEED 400000
509 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
510 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
511 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
512 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
513 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
514 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
516 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
517 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
520 #define CONFIG_SYS_I2C_FSL
521 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
522 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
527 #undef CONFIG_ID_EEPROM
529 #define CONFIG_RTC_PT7C4338
530 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
531 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
533 /* enable read and write access to EEPROM */
534 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
535 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
536 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
538 #if defined(CONFIG_PCI)
541 * Memory space is mapped 1-1, but I/O space must start from 0.
544 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
545 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
546 #ifdef CONFIG_PHYS_64BIT
547 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
549 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
551 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
552 #ifdef CONFIG_PHYS_64BIT
553 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
555 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
558 /* controller 1, Slot 2, tgtid 1, Base address a000 */
559 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
560 #ifdef CONFIG_PHYS_64BIT
561 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
563 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
565 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
566 #ifdef CONFIG_PHYS_64BIT
567 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
569 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
572 #if !defined(CONFIG_DM_PCI)
573 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
574 #define CONFIG_PCI_INDIRECT_BRIDGE
575 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
576 #ifdef CONFIG_PHYS_64BIT
577 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
579 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
581 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
582 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
583 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
585 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
586 #ifdef CONFIG_PHYS_64BIT
587 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
589 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
591 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
592 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
593 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
596 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
597 #endif /* CONFIG_PCI */
599 #if defined(CONFIG_TSEC_ENET)
601 #define CONFIG_TSEC1_NAME "eTSEC1"
603 #define CONFIG_TSEC2_NAME "eTSEC2"
605 #define CONFIG_TSEC3_NAME "eTSEC3"
607 #define TSEC1_PHY_ADDR 2
608 #define TSEC2_PHY_ADDR 0
609 #define TSEC3_PHY_ADDR 1
611 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
612 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
613 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
615 #define TSEC1_PHYIDX 0
616 #define TSEC2_PHYIDX 0
617 #define TSEC3_PHYIDX 0
619 #define CONFIG_ETHPRIME "eTSEC1"
621 #define CONFIG_HAS_ETH0
622 #define CONFIG_HAS_ETH1
623 #define CONFIG_HAS_ETH2
624 #endif /* CONFIG_TSEC_ENET */
627 /* QE microcode/firmware address */
628 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
629 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
630 #endif /* CONFIG_QE */
635 #if defined(CONFIG_SDCARD)
636 #define CONFIG_FSL_FIXED_MMC_LOCATION
637 #elif defined(CONFIG_MTD_RAW_NAND)
638 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
639 #ifdef CONFIG_TPL_BUILD
640 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
642 #elif defined(CONFIG_SYS_RAMBOOT)
643 #define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
646 #define CONFIG_LOADS_ECHO /* echo on for serial download */
647 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
652 #define CONFIG_HAS_FSL_DR_USB
654 #if defined(CONFIG_HAS_FSL_DR_USB)
655 #ifdef CONFIG_USB_EHCI_HCD
656 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
657 #define CONFIG_USB_EHCI_FSL
661 #if defined(CONFIG_TARGET_P1020RDB_PD)
662 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
666 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
669 #undef CONFIG_WATCHDOG /* watchdog disabled */
672 * Miscellaneous configurable options
674 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
677 * For booting Linux, the board info and command line data
678 * have to be in the first 64 MB of memory, since this is
679 * the maximum mapped by the Linux kernel during initialization.
681 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
682 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
684 #if defined(CONFIG_CMD_KGDB)
685 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
689 * Environment Configuration
691 #define CONFIG_HOSTNAME "unknown"
692 #define CONFIG_ROOTPATH "/opt/nfsroot"
693 #define CONFIG_BOOTFILE "uImage"
694 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
696 /* default location for tftp and bootm */
697 #define CONFIG_LOADADDR 1000000
700 #define __NOR_RST_CMD \
701 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
702 i2c mw 18 3 __SW_BOOT_MASK 1; reset
705 #define __SPI_RST_CMD \
706 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
707 i2c mw 18 3 __SW_BOOT_MASK 1; reset
710 #define __SD_RST_CMD \
711 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
712 i2c mw 18 3 __SW_BOOT_MASK 1; reset
714 #ifdef __SW_BOOT_NAND
715 #define __NAND_RST_CMD \
716 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
717 i2c mw 18 3 __SW_BOOT_MASK 1; reset
719 #ifdef __SW_BOOT_PCIE
720 #define __PCIE_RST_CMD \
721 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
722 i2c mw 18 3 __SW_BOOT_MASK 1; reset
725 #define CONFIG_EXTRA_ENV_SETTINGS \
727 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
728 "loadaddr=1000000\0" \
729 "bootfile=uImage\0" \
730 "tftpflash=tftpboot $loadaddr $uboot; " \
731 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
732 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
733 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
734 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
735 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
736 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
737 "consoledev=ttyS0\0" \
738 "ramdiskaddr=2000000\0" \
739 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
740 "fdtaddr=1e00000\0" \
742 "jffs2nor=mtdblock3\0" \
743 "norbootaddr=ef080000\0" \
744 "norfdtaddr=ef040000\0" \
745 "jffs2nand=mtdblock9\0" \
746 "nandbootaddr=100000\0" \
747 "nandfdtaddr=80000\0" \
748 "ramdisk_size=120000\0" \
749 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
750 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
751 __stringify(__VSCFW_ADDR)"\0" \
752 __stringify(__NOR_RST_CMD)"\0" \
753 __stringify(__SPI_RST_CMD)"\0" \
754 __stringify(__SD_RST_CMD)"\0" \
755 __stringify(__NAND_RST_CMD)"\0" \
756 __stringify(__PCIE_RST_CMD)"\0"
758 #define CONFIG_NFSBOOTCOMMAND \
759 "setenv bootargs root=/dev/nfs rw " \
760 "nfsroot=$serverip:$rootpath " \
761 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
762 "console=$consoledev,$baudrate $othbootargs;" \
763 "tftp $loadaddr $bootfile;" \
764 "tftp $fdtaddr $fdtfile;" \
765 "bootm $loadaddr - $fdtaddr"
767 #define CONFIG_HDBOOT \
768 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
769 "console=$consoledev,$baudrate $othbootargs;" \
771 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
772 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
773 "bootm $loadaddr - $fdtaddr"
775 #define CONFIG_USB_FAT_BOOT \
776 "setenv bootargs root=/dev/ram rw " \
777 "console=$consoledev,$baudrate $othbootargs " \
778 "ramdisk_size=$ramdisk_size;" \
780 "fatload usb 0:2 $loadaddr $bootfile;" \
781 "fatload usb 0:2 $fdtaddr $fdtfile;" \
782 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
783 "bootm $loadaddr $ramdiskaddr $fdtaddr"
785 #define CONFIG_USB_EXT2_BOOT \
786 "setenv bootargs root=/dev/ram rw " \
787 "console=$consoledev,$baudrate $othbootargs " \
788 "ramdisk_size=$ramdisk_size;" \
790 "ext2load usb 0:4 $loadaddr $bootfile;" \
791 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
792 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
793 "bootm $loadaddr $ramdiskaddr $fdtaddr"
795 #define CONFIG_NORBOOT \
796 "setenv bootargs root=/dev/$jffs2nor rw " \
797 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
798 "bootm $norbootaddr - $norfdtaddr"
800 #define CONFIG_RAMBOOTCOMMAND \
801 "setenv bootargs root=/dev/ram rw " \
802 "console=$consoledev,$baudrate $othbootargs " \
803 "ramdisk_size=$ramdisk_size;" \
804 "tftp $ramdiskaddr $ramdiskfile;" \
805 "tftp $loadaddr $bootfile;" \
806 "tftp $fdtaddr $fdtfile;" \
807 "bootm $loadaddr $ramdiskaddr $fdtaddr"
809 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
811 #endif /* __CONFIG_H */