1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * QorIQ RDB boards configuration file
13 #include <linux/stringify.h>
15 #if defined(CONFIG_TARGET_P1020RDB_PC)
16 #define CONFIG_BOARDNAME "P1020RDB-PC"
17 #define CONFIG_NAND_FSL_ELBC
18 #define CONFIG_VSC7385_ENET
20 #define __SW_BOOT_MASK 0x03
21 #define __SW_BOOT_NOR 0x5c
22 #define __SW_BOOT_SPI 0x1c
23 #define __SW_BOOT_SD 0x9c
24 #define __SW_BOOT_NAND 0xec
25 #define __SW_BOOT_PCIE 0x6c
26 #define CONFIG_SYS_L2_SIZE (256 << 10)
30 * P1020RDB-PD board has user selectable switches for evaluating different
31 * frequency and boot options for the P1020 device. The table that
32 * follow describe the available options. The front six binary number was in
33 * accordance with SW3[1:6].
34 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
35 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
36 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
37 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
38 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
39 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
40 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
42 #if defined(CONFIG_TARGET_P1020RDB_PD)
43 #define CONFIG_BOARDNAME "P1020RDB-PD"
44 #define CONFIG_NAND_FSL_ELBC
45 #define CONFIG_VSC7385_ENET
47 #define __SW_BOOT_MASK 0x03
48 #define __SW_BOOT_NOR 0x64
49 #define __SW_BOOT_SPI 0x34
50 #define __SW_BOOT_SD 0x24
51 #define __SW_BOOT_NAND 0x44
52 #define __SW_BOOT_PCIE 0x74
53 #define CONFIG_SYS_L2_SIZE (256 << 10)
55 * Dynamic MTD Partition support with mtdparts
59 #if defined(CONFIG_TARGET_P1024RDB)
60 #define CONFIG_BOARDNAME "P1024RDB"
61 #define CONFIG_NAND_FSL_ELBC
63 #define __SW_BOOT_MASK 0xf3
64 #define __SW_BOOT_NOR 0x00
65 #define __SW_BOOT_SPI 0x08
66 #define __SW_BOOT_SD 0x04
67 #define __SW_BOOT_NAND 0x0c
68 #define CONFIG_SYS_L2_SIZE (256 << 10)
71 #if defined(CONFIG_TARGET_P2020RDB)
72 #define CONFIG_BOARDNAME "P2020RDB-PC"
73 #define CONFIG_NAND_FSL_ELBC
74 #define CONFIG_VSC7385_ENET
75 #define __SW_BOOT_MASK 0x03
76 #define __SW_BOOT_NOR 0xc8
77 #define __SW_BOOT_SPI 0x28
78 #define __SW_BOOT_SD 0x68 /* or 0x18 */
79 #define __SW_BOOT_NAND 0xe8
80 #define __SW_BOOT_PCIE 0xa8
81 #define CONFIG_SYS_L2_SIZE (512 << 10)
83 * Dynamic MTD Partition support with mtdparts
88 #define CONFIG_SPL_FLUSH_IMAGE
89 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
90 #define CONFIG_SPL_PAD_TO 0x20000
91 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
92 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
93 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
94 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
95 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
96 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
97 #ifdef CONFIG_SPL_BUILD
98 #define CONFIG_SPL_COMMON_INIT_DDR
102 #ifdef CONFIG_SPIFLASH
103 #define CONFIG_SPL_SPI_FLASH_MINIMAL
104 #define CONFIG_SPL_FLUSH_IMAGE
105 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
106 #define CONFIG_SPL_PAD_TO 0x20000
107 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
108 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
109 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
110 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
111 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
112 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
113 #ifdef CONFIG_SPL_BUILD
114 #define CONFIG_SPL_COMMON_INIT_DDR
118 #ifdef CONFIG_MTD_RAW_NAND
119 #ifdef CONFIG_TPL_BUILD
120 #define CONFIG_SPL_FLUSH_IMAGE
121 #define CONFIG_SPL_NAND_INIT
122 #define CONFIG_SPL_COMMON_INIT_DDR
123 #define CONFIG_SPL_MAX_SIZE (128 << 10)
124 #define CONFIG_TPL_TEXT_BASE 0xf8f81000
125 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
126 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
127 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
128 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
129 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
130 #elif defined(CONFIG_SPL_BUILD)
131 #define CONFIG_SPL_INIT_MINIMAL
132 #define CONFIG_SPL_FLUSH_IMAGE
133 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
134 #define CONFIG_SPL_MAX_SIZE 4096
135 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
136 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
137 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
138 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
139 #endif /* not CONFIG_TPL_BUILD */
141 #define CONFIG_SPL_PAD_TO 0x20000
142 #define CONFIG_TPL_PAD_TO 0x20000
143 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
146 #ifndef CONFIG_RESET_VECTOR_ADDRESS
147 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
150 #ifndef CONFIG_SYS_MONITOR_BASE
151 #ifdef CONFIG_TPL_BUILD
152 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
153 #elif defined(CONFIG_SPL_BUILD)
154 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
156 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
160 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
161 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
162 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
164 #define CONFIG_SYS_SATA_MAX_DEVICE 2
167 #if defined(CONFIG_TARGET_P2020RDB)
168 #define CONFIG_SYS_CLK_FREQ 100000000
170 #define CONFIG_SYS_CLK_FREQ 66666666
172 #define CONFIG_DDR_CLK_FREQ 66666666
174 #define CONFIG_HWCONFIG
176 * These can be toggled for performance analysis, otherwise use default.
178 #define CONFIG_L2_CACHE
181 #define CONFIG_ENABLE_36BIT_PHYS
183 #define CONFIG_SYS_CCSRBAR 0xffe00000
184 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
186 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
188 #ifdef CONFIG_SPL_BUILD
189 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
193 #define CONFIG_SYS_DDR_RAW_TIMING
194 #define CONFIG_DDR_SPD
195 #define CONFIG_SYS_SPD_BUS_NUM 1
196 #define SPD_EEPROM_ADDRESS 0x52
198 #if defined(CONFIG_TARGET_P1020RDB_PD)
199 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
200 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
202 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
203 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
205 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
206 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
207 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
209 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
211 /* Default settings for DDR3 */
212 #ifndef CONFIG_TARGET_P2020RDB
213 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
214 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
215 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
216 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
217 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
218 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
220 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
221 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
222 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
223 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
225 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
226 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
227 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
228 #define CONFIG_SYS_DDR_RCW_1 0x00000000
229 #define CONFIG_SYS_DDR_RCW_2 0x00000000
230 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
231 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
232 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
233 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
235 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
236 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
237 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
238 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
239 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
240 #define CONFIG_SYS_DDR_MODE_1 0x40461520
241 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
242 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
248 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
249 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
250 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
251 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
253 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
254 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
255 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
256 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
257 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
258 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
259 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
263 * Local Bus Definitions
265 #if defined(CONFIG_TARGET_P1020RDB_PD)
266 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
267 #define CONFIG_SYS_FLASH_BASE 0xec000000
269 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
270 #define CONFIG_SYS_FLASH_BASE 0xef000000
273 #ifdef CONFIG_PHYS_64BIT
274 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
276 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
279 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
282 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
284 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
285 #define CONFIG_SYS_FLASH_QUIET_TEST
286 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
288 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
290 #undef CONFIG_SYS_FLASH_CHECKSUM
291 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
292 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
294 #define CONFIG_SYS_FLASH_EMPTY_INFO
297 #ifdef CONFIG_NAND_FSL_ELBC
298 #define CONFIG_SYS_NAND_BASE 0xff800000
299 #ifdef CONFIG_PHYS_64BIT
300 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
302 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
305 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
306 #define CONFIG_SYS_MAX_NAND_DEVICE 1
307 #if defined(CONFIG_TARGET_P1020RDB_PD)
308 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
310 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
313 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
314 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
315 | BR_PS_8 /* Port Size = 8 bit */ \
316 | BR_MS_FCM /* MSEL = FCM */ \
318 #if defined(CONFIG_TARGET_P1020RDB_PD)
319 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
320 | OR_FCM_PGS /* Large Page*/ \
328 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
336 #endif /* CONFIG_NAND_FSL_ELBC */
338 #define CONFIG_SYS_INIT_RAM_LOCK
339 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
340 #ifdef CONFIG_PHYS_64BIT
341 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
342 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
343 /* The assembler doesn't like typecast */
344 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
345 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
346 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
348 /* Initial L1 address */
349 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
350 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
351 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
353 /* Size of used area in RAM */
354 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
356 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
357 GENERATED_GBL_DATA_SIZE)
358 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
360 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
361 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
363 #define CONFIG_SYS_CPLD_BASE 0xffa00000
364 #ifdef CONFIG_PHYS_64BIT
365 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
367 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
369 /* CPLD config size: 1Mb */
370 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
372 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
374 #define CONFIG_SYS_PMC_BASE 0xff980000
375 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
376 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
378 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
379 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
382 #ifdef CONFIG_MTD_RAW_NAND
383 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
384 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
385 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
386 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
388 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
389 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
390 #ifdef CONFIG_NAND_FSL_ELBC
391 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
392 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
395 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
396 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
399 #ifdef CONFIG_VSC7385_ENET
400 #define __VSCFW_ADDR "vscfw_addr=ef000000"
401 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
403 #ifdef CONFIG_PHYS_64BIT
404 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
406 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
409 #define CONFIG_SYS_VSC7385_BR_PRELIM \
410 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
411 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
412 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
413 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
415 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
416 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
418 /* The size of the VSC7385 firmware image */
419 #define CONFIG_VSC7385_IMAGE_SIZE 8192
423 * Config the L2 Cache as L2 SRAM
425 #if defined(CONFIG_SPL_BUILD)
426 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
427 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
428 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
429 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
430 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
431 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
432 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
433 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
434 #if defined(CONFIG_TARGET_P2020RDB)
435 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
437 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
439 #elif defined(CONFIG_MTD_RAW_NAND)
440 #ifdef CONFIG_TPL_BUILD
441 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
442 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
443 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
444 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
445 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
446 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
447 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
448 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
450 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
451 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
452 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
453 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
454 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
455 #endif /* CONFIG_TPL_BUILD */
459 /* Serial Port - controlled on board with jumper J8
463 #undef CONFIG_SERIAL_SOFTWARE_FIFO
464 #define CONFIG_SYS_NS16550_SERIAL
465 #define CONFIG_SYS_NS16550_REG_SIZE 1
466 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
467 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
468 #define CONFIG_NS16550_MIN_FUNCTIONS
471 #define CONFIG_SYS_BAUDRATE_TABLE \
472 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
474 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
475 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
478 #ifndef CONFIG_DM_I2C
479 #define CONFIG_SYS_I2C
480 #define CONFIG_SYS_FSL_I2C_SPEED 400000
481 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
482 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
483 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
484 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
485 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
486 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
488 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
489 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
492 #define CONFIG_SYS_I2C_FSL
493 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
494 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
499 #undef CONFIG_ID_EEPROM
501 #define CONFIG_RTC_PT7C4338
502 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
503 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
505 /* enable read and write access to EEPROM */
506 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
507 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
508 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
510 #if defined(CONFIG_PCI)
513 * Memory space is mapped 1-1, but I/O space must start from 0.
516 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
517 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
518 #ifdef CONFIG_PHYS_64BIT
519 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
521 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
523 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
524 #ifdef CONFIG_PHYS_64BIT
525 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
527 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
530 /* controller 1, Slot 2, tgtid 1, Base address a000 */
531 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
532 #ifdef CONFIG_PHYS_64BIT
533 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
535 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
537 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
538 #ifdef CONFIG_PHYS_64BIT
539 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
541 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
544 #if !defined(CONFIG_DM_PCI)
545 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
546 #define CONFIG_PCI_INDIRECT_BRIDGE
547 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
548 #ifdef CONFIG_PHYS_64BIT
549 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
551 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
553 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
554 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
555 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
557 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
558 #ifdef CONFIG_PHYS_64BIT
559 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
561 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
563 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
564 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
565 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
568 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
569 #endif /* CONFIG_PCI */
571 #if defined(CONFIG_TSEC_ENET)
573 #define CONFIG_TSEC1_NAME "eTSEC1"
575 #define CONFIG_TSEC2_NAME "eTSEC2"
577 #define CONFIG_TSEC3_NAME "eTSEC3"
579 #define TSEC1_PHY_ADDR 2
580 #define TSEC2_PHY_ADDR 0
581 #define TSEC3_PHY_ADDR 1
583 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
584 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
585 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
587 #define TSEC1_PHYIDX 0
588 #define TSEC2_PHYIDX 0
589 #define TSEC3_PHYIDX 0
591 #define CONFIG_ETHPRIME "eTSEC1"
593 #define CONFIG_HAS_ETH0
594 #define CONFIG_HAS_ETH1
595 #define CONFIG_HAS_ETH2
596 #endif /* CONFIG_TSEC_ENET */
599 /* QE microcode/firmware address */
600 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
601 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
602 #endif /* CONFIG_QE */
607 #if defined(CONFIG_SDCARD)
608 #define CONFIG_FSL_FIXED_MMC_LOCATION
609 #elif defined(CONFIG_MTD_RAW_NAND)
610 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
611 #ifdef CONFIG_TPL_BUILD
612 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
614 #elif defined(CONFIG_SYS_RAMBOOT)
615 #define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
618 #define CONFIG_LOADS_ECHO /* echo on for serial download */
619 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
624 #define CONFIG_HAS_FSL_DR_USB
626 #if defined(CONFIG_HAS_FSL_DR_USB)
627 #ifdef CONFIG_USB_EHCI_HCD
628 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
629 #define CONFIG_USB_EHCI_FSL
633 #if defined(CONFIG_TARGET_P1020RDB_PD)
634 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
638 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
641 #undef CONFIG_WATCHDOG /* watchdog disabled */
644 * Miscellaneous configurable options
646 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
649 * For booting Linux, the board info and command line data
650 * have to be in the first 64 MB of memory, since this is
651 * the maximum mapped by the Linux kernel during initialization.
653 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
654 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
656 #if defined(CONFIG_CMD_KGDB)
657 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
661 * Environment Configuration
663 #define CONFIG_HOSTNAME "unknown"
664 #define CONFIG_ROOTPATH "/opt/nfsroot"
665 #define CONFIG_BOOTFILE "uImage"
666 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
668 /* default location for tftp and bootm */
669 #define CONFIG_LOADADDR 1000000
672 #define __NOR_RST_CMD \
673 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
674 i2c mw 18 3 __SW_BOOT_MASK 1; reset
677 #define __SPI_RST_CMD \
678 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
679 i2c mw 18 3 __SW_BOOT_MASK 1; reset
682 #define __SD_RST_CMD \
683 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
684 i2c mw 18 3 __SW_BOOT_MASK 1; reset
686 #ifdef __SW_BOOT_NAND
687 #define __NAND_RST_CMD \
688 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
689 i2c mw 18 3 __SW_BOOT_MASK 1; reset
691 #ifdef __SW_BOOT_PCIE
692 #define __PCIE_RST_CMD \
693 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
694 i2c mw 18 3 __SW_BOOT_MASK 1; reset
697 #define CONFIG_EXTRA_ENV_SETTINGS \
699 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
700 "loadaddr=1000000\0" \
701 "bootfile=uImage\0" \
702 "tftpflash=tftpboot $loadaddr $uboot; " \
703 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
704 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
705 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
706 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
707 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
708 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
709 "consoledev=ttyS0\0" \
710 "ramdiskaddr=2000000\0" \
711 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
712 "fdtaddr=1e00000\0" \
714 "jffs2nor=mtdblock3\0" \
715 "norbootaddr=ef080000\0" \
716 "norfdtaddr=ef040000\0" \
717 "jffs2nand=mtdblock9\0" \
718 "nandbootaddr=100000\0" \
719 "nandfdtaddr=80000\0" \
720 "ramdisk_size=120000\0" \
721 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
722 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
723 __stringify(__VSCFW_ADDR)"\0" \
724 __stringify(__NOR_RST_CMD)"\0" \
725 __stringify(__SPI_RST_CMD)"\0" \
726 __stringify(__SD_RST_CMD)"\0" \
727 __stringify(__NAND_RST_CMD)"\0" \
728 __stringify(__PCIE_RST_CMD)"\0"
730 #define CONFIG_NFSBOOTCOMMAND \
731 "setenv bootargs root=/dev/nfs rw " \
732 "nfsroot=$serverip:$rootpath " \
733 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
734 "console=$consoledev,$baudrate $othbootargs;" \
735 "tftp $loadaddr $bootfile;" \
736 "tftp $fdtaddr $fdtfile;" \
737 "bootm $loadaddr - $fdtaddr"
739 #define CONFIG_HDBOOT \
740 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
741 "console=$consoledev,$baudrate $othbootargs;" \
743 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
744 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
745 "bootm $loadaddr - $fdtaddr"
747 #define CONFIG_USB_FAT_BOOT \
748 "setenv bootargs root=/dev/ram rw " \
749 "console=$consoledev,$baudrate $othbootargs " \
750 "ramdisk_size=$ramdisk_size;" \
752 "fatload usb 0:2 $loadaddr $bootfile;" \
753 "fatload usb 0:2 $fdtaddr $fdtfile;" \
754 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
755 "bootm $loadaddr $ramdiskaddr $fdtaddr"
757 #define CONFIG_USB_EXT2_BOOT \
758 "setenv bootargs root=/dev/ram rw " \
759 "console=$consoledev,$baudrate $othbootargs " \
760 "ramdisk_size=$ramdisk_size;" \
762 "ext2load usb 0:4 $loadaddr $bootfile;" \
763 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
764 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
765 "bootm $loadaddr $ramdiskaddr $fdtaddr"
767 #define CONFIG_NORBOOT \
768 "setenv bootargs root=/dev/$jffs2nor rw " \
769 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
770 "bootm $norbootaddr - $norfdtaddr"
772 #define CONFIG_RAMBOOTCOMMAND \
773 "setenv bootargs root=/dev/ram rw " \
774 "console=$consoledev,$baudrate $othbootargs " \
775 "ramdisk_size=$ramdisk_size;" \
776 "tftp $ramdiskaddr $ramdiskfile;" \
777 "tftp $loadaddr $bootfile;" \
778 "tftp $fdtaddr $fdtfile;" \
779 "bootm $loadaddr $ramdiskaddr $fdtaddr"
781 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
783 #endif /* __CONFIG_H */