1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * QorIQ RDB boards configuration file
13 #include <linux/stringify.h>
15 #if defined(CONFIG_TARGET_P1020RDB_PC)
17 #define __SW_BOOT_MASK 0x03
18 #define __SW_BOOT_NOR 0x5c
19 #define __SW_BOOT_SPI 0x1c
20 #define __SW_BOOT_SD 0x9c
21 #define __SW_BOOT_NAND 0xec
22 #define __SW_BOOT_PCIE 0x6c
23 #define __SW_NOR_BANK_MASK 0xfd
24 #define __SW_NOR_BANK_UP 0x00
25 #define __SW_NOR_BANK_LO 0x02
26 #define __SW_BOOT_NOR_BANK_UP 0x5c /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
27 #define __SW_BOOT_NOR_BANK_LO 0x5e /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
28 #define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
32 * P1020RDB-PD board has user selectable switches for evaluating different
33 * frequency and boot options for the P1020 device. The table that
34 * follow describe the available options. The front six binary number was in
35 * accordance with SW3[1:6].
36 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
37 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
38 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
39 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
40 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
41 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
42 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
44 #if defined(CONFIG_TARGET_P1020RDB_PD)
46 #define __SW_BOOT_MASK 0x03
47 #define __SW_BOOT_NOR 0x64
48 #define __SW_BOOT_SPI 0x34
49 #define __SW_BOOT_SD 0x24
50 #define __SW_BOOT_NAND 0x44
51 #define __SW_BOOT_PCIE 0x74
52 #define __SW_NOR_BANK_MASK 0xfd
53 #define __SW_NOR_BANK_UP 0x00
54 #define __SW_NOR_BANK_LO 0x02
55 #define __SW_BOOT_NOR_BANK_UP 0x64 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
56 #define __SW_BOOT_NOR_BANK_LO 0x66 /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
57 #define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
59 * Dynamic MTD Partition support with mtdparts
63 #if defined(CONFIG_TARGET_P2020RDB)
64 #define __SW_BOOT_MASK 0x03
65 #define __SW_BOOT_NOR 0xc8
66 #define __SW_BOOT_SPI 0x28
67 #define __SW_BOOT_SD 0x68
68 #define __SW_BOOT_SD2 0x18
69 #define __SW_BOOT_NAND 0xe8
70 #define __SW_BOOT_PCIE 0xa8
71 #define __SW_NOR_BANK_MASK 0xfd
72 #define __SW_NOR_BANK_UP 0x00
73 #define __SW_NOR_BANK_LO 0x02
74 #define __SW_BOOT_NOR_BANK_UP 0xc8 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
75 #define __SW_BOOT_NOR_BANK_LO 0xca /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
76 #define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
78 * Dynamic MTD Partition support with mtdparts
83 #define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
84 #define CFG_SYS_MMC_U_BOOT_DST CONFIG_TEXT_BASE
85 #define CFG_SYS_MMC_U_BOOT_START CONFIG_TEXT_BASE
86 #ifdef CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR
87 #define CFG_SYS_MMC_U_BOOT_OFFS (CONFIG_SPL_PAD_TO - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA*512)
89 #define CFG_SYS_MMC_U_BOOT_OFFS CONFIG_SPL_PAD_TO
91 #elif defined(CONFIG_SPIFLASH)
92 #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
93 #define CFG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_TEXT_BASE
94 #define CFG_SYS_SPI_FLASH_U_BOOT_START CONFIG_TEXT_BASE
95 #define CFG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SPL_PAD_TO
96 #elif defined(CONFIG_MTD_RAW_NAND)
97 #ifdef CONFIG_TPL_BUILD
98 #define CFG_SYS_NAND_U_BOOT_SIZE (832 << 10)
99 #define CFG_SYS_NAND_U_BOOT_DST (0x11000000)
100 #define CFG_SYS_NAND_U_BOOT_START (0x11000000)
101 #elif defined(CONFIG_SPL_BUILD)
102 #define CFG_SYS_NAND_U_BOOT_SIZE (128 << 10)
103 #define CFG_SYS_NAND_U_BOOT_DST 0xf8f80000
104 #define CFG_SYS_NAND_U_BOOT_START 0xf8f80000
105 #endif /* not CONFIG_TPL_BUILD */
108 #ifndef CONFIG_RESET_VECTOR_ADDRESS
109 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
113 * These can be toggled for performance analysis, otherwise use default.
115 #define CONFIG_L2_CACHE
117 #define CFG_SYS_CCSRBAR 0xffe00000
118 #define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
121 #define SPD_EEPROM_ADDRESS 0x52
123 #if defined(CONFIG_TARGET_P1020RDB_PD)
124 #define CFG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
126 #define CFG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
128 #define CFG_SYS_SDRAM_SIZE (1u << (CFG_SYS_SDRAM_SIZE_LAW - 19))
129 #define CFG_SYS_DDR_SDRAM_BASE 0x00000000
130 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
132 /* Default settings for DDR3 */
133 #ifndef CONFIG_TARGET_P2020RDB
134 #define CFG_SYS_DDR_CS0_BNDS 0x0000003f
135 #define CFG_SYS_DDR_CS0_CONFIG 0x80014302
136 #define CFG_SYS_DDR_CS0_CONFIG_2 0x00000000
137 #define CFG_SYS_DDR_CS1_BNDS 0x0040007f
138 #define CFG_SYS_DDR_CS1_CONFIG 0x80014302
139 #define CFG_SYS_DDR_CS1_CONFIG_2 0x00000000
141 #define CFG_SYS_DDR_INIT_ADDR 0x00000000
142 #define CFG_SYS_DDR_INIT_EXT_ADDR 0x00000000
143 #define CFG_SYS_DDR_MODE_CONTROL 0x00000000
145 #define CFG_SYS_DDR_ZQ_CONTROL 0x89080600
146 #define CFG_SYS_DDR_WRLVL_CONTROL 0x8655A608
147 #define CFG_SYS_DDR_SR_CNTR 0x00000000
148 #define CFG_SYS_DDR_RCW_1 0x00000000
149 #define CFG_SYS_DDR_RCW_2 0x00000000
150 #define CFG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
151 #define CFG_SYS_DDR_CONTROL_2 0x04401050
152 #define CFG_SYS_DDR_TIMING_4 0x00220001
153 #define CFG_SYS_DDR_TIMING_5 0x03402400
155 #define CFG_SYS_DDR_TIMING_3 0x00020000
156 #define CFG_SYS_DDR_TIMING_0 0x00330004
157 #define CFG_SYS_DDR_TIMING_1 0x6f6B4846
158 #define CFG_SYS_DDR_TIMING_2 0x0FA8C8CF
159 #define CFG_SYS_DDR_CLK_CTRL 0x03000000
160 #define CFG_SYS_DDR_MODE_1 0x40461520
161 #define CFG_SYS_DDR_MODE_2 0x8000c000
162 #define CFG_SYS_DDR_INTERVAL 0x0C300000
168 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
169 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
170 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
171 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
173 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
174 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
175 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
176 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
177 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
178 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
182 * Local Bus Definitions
184 #if defined(CONFIG_TARGET_P1020RDB_PD)
185 #define CFG_SYS_FLASH_BASE 0xec000000
187 #define CFG_SYS_FLASH_BASE 0xef000000
190 #ifdef CONFIG_PHYS_64BIT
191 #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
193 #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
196 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) \
199 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
201 #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
202 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
205 #ifdef CONFIG_NAND_FSL_ELBC
206 #define CFG_SYS_NAND_BASE 0xff800000
207 #ifdef CONFIG_PHYS_64BIT
208 #define CFG_SYS_NAND_BASE_PHYS 0xfff800000ull
210 #define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
213 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
215 #define CFG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
216 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
217 | BR_PS_8 /* Port Size = 8 bit */ \
218 | BR_MS_FCM /* MSEL = FCM */ \
220 #if defined(CONFIG_TARGET_P1020RDB_PD)
221 #define CFG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
222 | OR_FCM_PGS /* Large Page*/ \
230 #define CFG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
238 #endif /* CONFIG_NAND_FSL_ELBC */
240 #define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
241 #ifdef CONFIG_PHYS_64BIT
242 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
243 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR
244 /* The assembler doesn't like typecast */
245 #define CFG_SYS_INIT_RAM_ADDR_PHYS \
246 ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
247 CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
249 /* Initial L1 address */
250 #define CFG_SYS_INIT_RAM_ADDR_PHYS CFG_SYS_INIT_RAM_ADDR
251 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
252 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS
254 /* Size of used area in RAM */
255 #define CFG_SYS_INIT_RAM_SIZE 0x00004000
257 #define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
259 #define CFG_SYS_CPLD_BASE 0xffa00000
260 #ifdef CONFIG_PHYS_64BIT
261 #define CFG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
263 #define CFG_SYS_CPLD_BASE_PHYS CFG_SYS_CPLD_BASE
265 /* CPLD config size: 1Mb */
268 #ifdef CONFIG_VSC7385_ENET
269 #define __VSCFW_ADDR "vscfw_addr=ef000000\0"
270 #define CFG_SYS_VSC7385_BASE 0xffb00000
272 #ifdef CONFIG_PHYS_64BIT
273 #define CFG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
275 #define CFG_SYS_VSC7385_BASE_PHYS CFG_SYS_VSC7385_BASE
278 /* The size of the VSC7385 firmware image */
279 #define CONFIG_VSC7385_IMAGE_SIZE 8192
283 #define __VSCFW_ADDR ""
287 * Config the L2 Cache as L2 SRAM
289 #if defined(CONFIG_SPL_BUILD)
290 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
291 #define CFG_SYS_INIT_L2_ADDR 0xf8f80000
292 #define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
293 #define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
294 #elif defined(CONFIG_MTD_RAW_NAND)
295 #ifdef CONFIG_TPL_BUILD
296 #define CFG_SYS_INIT_L2_ADDR 0xf8f80000
297 #define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
298 #define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
300 #define CFG_SYS_INIT_L2_ADDR 0xf8f80000
301 #define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
302 #define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
303 #endif /* CONFIG_TPL_BUILD */
307 /* Serial Port - controlled on board with jumper J8
311 #undef CONFIG_SERIAL_SOFTWARE_FIFO
312 #define CFG_SYS_NS16550_CLK get_bus_freq(0)
314 #define CFG_SYS_BAUDRATE_TABLE \
315 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
317 #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500)
318 #define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600)
321 #if !CONFIG_IS_ENABLED(DM_I2C)
322 #define CFG_SYS_I2C_NOPROBES { {0, 0x29} }
329 #define CFG_SYS_I2C_RTC_ADDR 0x68
330 #define CFG_SYS_I2C_PCA9557_ADDR 0x18
332 /* enable read and write access to EEPROM */
334 #if defined(CONFIG_PCI)
337 * Memory space is mapped 1-1, but I/O space must start from 0.
340 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
341 #define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000
342 #ifdef CONFIG_PHYS_64BIT
343 #define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
345 #define CFG_SYS_PCIE2_MEM_PHYS 0xa0000000
347 #define CFG_SYS_PCIE2_IO_VIRT 0xffc10000
348 #ifdef CONFIG_PHYS_64BIT
349 #define CFG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
351 #define CFG_SYS_PCIE2_IO_PHYS 0xffc10000
354 /* controller 1, Slot 2, tgtid 1, Base address a000 */
355 #define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
356 #ifdef CONFIG_PHYS_64BIT
357 #define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
359 #define CFG_SYS_PCIE1_MEM_PHYS 0x80000000
361 #define CFG_SYS_PCIE1_IO_VIRT 0xffc00000
362 #ifdef CONFIG_PHYS_64BIT
363 #define CFG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
365 #define CFG_SYS_PCIE1_IO_PHYS 0xffc00000
367 #endif /* CONFIG_PCI */
372 #if defined(CONFIG_MTD_RAW_NAND)
373 #ifdef CONFIG_TPL_BUILD
374 #define SPL_ENV_ADDR (CFG_SYS_INIT_L2_ADDR + (160 << 10))
383 #define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
387 * Miscellaneous configurable options
391 * For booting Linux, the board info and command line data
392 * have to be in the first 64 MB of memory, since this is
393 * the maximum mapped by the Linux kernel during initialization.
395 #define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
398 * Environment Configuration
400 #define CONFIG_HOSTNAME "unknown"
401 #define CONFIG_ROOTPATH "/opt/nfsroot"
402 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
404 #include "p1_p2_bootsrc.h"
406 #define CONFIG_EXTRA_ENV_SETTINGS \
408 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
409 "loadaddr=1000000\0" \
410 "bootfile=uImage\0" \
411 "tftpflash=tftpboot $loadaddr $uboot; " \
412 "protect off " __stringify(CONFIG_TEXT_BASE) " +$filesize; " \
413 "erase " __stringify(CONFIG_TEXT_BASE) " +$filesize; " \
414 "cp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) " $filesize; " \
415 "protect on " __stringify(CONFIG_TEXT_BASE) " +$filesize; " \
416 "cmp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) " $filesize\0" \
417 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
418 "consoledev=ttyS0\0" \
419 "ramdiskaddr=2000000\0" \
420 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
421 "fdtaddr=1e00000\0" \
423 "jffs2nor=mtdblock3\0" \
424 "norbootaddr=ef080000\0" \
425 "norfdtaddr=ef040000\0" \
426 "jffs2nand=mtdblock9\0" \
427 "nandbootaddr=100000\0" \
428 "nandfdtaddr=80000\0" \
429 "ramdisk_size=120000\0" \
431 MAP_NOR_LO_CMD(map_lowernorbank) \
432 MAP_NOR_UP_CMD(map_uppernorbank) \
433 RST_NOR_CMD(norboot) \
434 RST_NOR_LO_CMD(norlowerboot) \
435 RST_NOR_UP_CMD(norupperboot) \
436 RST_SPI_CMD(spiboot) \
438 RST_SD2_CMD(sd2boot) \
439 RST_NAND_CMD(nandboot) \
440 RST_PCIE_CMD(pciboot) \
441 RST_DEF_CMD(defboot) \
444 #define CONFIG_USB_FAT_BOOT \
445 "setenv bootargs root=/dev/ram rw " \
446 "console=$consoledev,$baudrate $othbootargs " \
447 "ramdisk_size=$ramdisk_size;" \
449 "fatload usb 0:2 $loadaddr $bootfile;" \
450 "fatload usb 0:2 $fdtaddr $fdtfile;" \
451 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
452 "bootm $loadaddr $ramdiskaddr $fdtaddr"
454 #define CONFIG_USB_EXT2_BOOT \
455 "setenv bootargs root=/dev/ram rw " \
456 "console=$consoledev,$baudrate $othbootargs " \
457 "ramdisk_size=$ramdisk_size;" \
459 "ext2load usb 0:4 $loadaddr $bootfile;" \
460 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
461 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
462 "bootm $loadaddr $ramdiskaddr $fdtaddr"
464 #define CONFIG_NORBOOT \
465 "setenv bootargs root=/dev/$jffs2nor rw " \
466 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
467 "bootm $norbootaddr - $norfdtaddr"
469 #endif /* __CONFIG_H */