1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * QorIQ RDB boards configuration file
13 #include <linux/stringify.h>
15 #if defined(CONFIG_TARGET_P1020RDB_PC)
16 #define CONFIG_VSC7385_ENET
18 #define __SW_BOOT_MASK 0x03
19 #define __SW_BOOT_NOR 0x5c
20 #define __SW_BOOT_SPI 0x1c
21 #define __SW_BOOT_SD 0x9c
22 #define __SW_BOOT_NAND 0xec
23 #define __SW_BOOT_PCIE 0x6c
24 #define CONFIG_SYS_L2_SIZE (256 << 10)
28 * P1020RDB-PD board has user selectable switches for evaluating different
29 * frequency and boot options for the P1020 device. The table that
30 * follow describe the available options. The front six binary number was in
31 * accordance with SW3[1:6].
32 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
33 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
34 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
35 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
36 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
37 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
38 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
40 #if defined(CONFIG_TARGET_P1020RDB_PD)
41 #define CONFIG_VSC7385_ENET
43 #define __SW_BOOT_MASK 0x03
44 #define __SW_BOOT_NOR 0x64
45 #define __SW_BOOT_SPI 0x34
46 #define __SW_BOOT_SD 0x24
47 #define __SW_BOOT_NAND 0x44
48 #define __SW_BOOT_PCIE 0x74
49 #define CONFIG_SYS_L2_SIZE (256 << 10)
51 * Dynamic MTD Partition support with mtdparts
55 #if defined(CONFIG_TARGET_P2020RDB)
56 #define CONFIG_VSC7385_ENET
57 #define __SW_BOOT_MASK 0x03
58 #define __SW_BOOT_NOR 0xc8
59 #define __SW_BOOT_SPI 0x28
60 #define __SW_BOOT_SD 0x68
61 #define __SW_BOOT_SD2 0x18
62 #define __SW_BOOT_NAND 0xe8
63 #define __SW_BOOT_PCIE 0xa8
64 #define CONFIG_SYS_L2_SIZE (512 << 10)
66 * Dynamic MTD Partition support with mtdparts
71 #define CONFIG_SPL_FLUSH_IMAGE
72 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
73 #define CONFIG_SPL_PAD_TO 0x20000
74 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
75 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
76 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
77 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
78 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
79 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
80 #ifdef CONFIG_SPL_BUILD
81 #define CONFIG_SPL_COMMON_INIT_DDR
83 #elif defined(CONFIG_SPIFLASH)
84 #define CONFIG_SPL_SPI_FLASH_MINIMAL
85 #define CONFIG_SPL_FLUSH_IMAGE
86 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
87 #define CONFIG_SPL_PAD_TO 0x20000
88 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
89 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
90 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
91 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
92 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
93 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
94 #ifdef CONFIG_SPL_BUILD
95 #define CONFIG_SPL_COMMON_INIT_DDR
97 #elif defined(CONFIG_MTD_RAW_NAND)
98 #ifdef CONFIG_TPL_BUILD
99 #define CONFIG_SPL_FLUSH_IMAGE
100 #define CONFIG_SPL_NAND_INIT
101 #define CONFIG_SPL_COMMON_INIT_DDR
102 #define CONFIG_SPL_MAX_SIZE (128 << 10)
103 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
104 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
105 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
106 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
107 #elif defined(CONFIG_SPL_BUILD)
108 #define CONFIG_SPL_INIT_MINIMAL
109 #define CONFIG_SPL_FLUSH_IMAGE
110 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
111 #define CONFIG_SPL_MAX_SIZE 4096
112 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
113 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
114 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
116 #ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
117 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
119 #endif /* not CONFIG_TPL_BUILD */
121 #define CONFIG_SPL_PAD_TO 0x20000
122 #define CONFIG_TPL_PAD_TO 0x20000
123 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
126 #ifndef CONFIG_RESET_VECTOR_ADDRESS
127 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
130 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
131 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
135 #define CONFIG_HWCONFIG
137 * These can be toggled for performance analysis, otherwise use default.
139 #define CONFIG_L2_CACHE
141 #define CONFIG_ENABLE_36BIT_PHYS
143 #define CONFIG_SYS_CCSRBAR 0xffe00000
144 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
146 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
148 #ifdef CONFIG_SPL_BUILD
149 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
153 #define CONFIG_SYS_DDR_RAW_TIMING
154 #define CONFIG_SYS_SPD_BUS_NUM 1
155 #define SPD_EEPROM_ADDRESS 0x52
157 #if defined(CONFIG_TARGET_P1020RDB_PD)
158 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
160 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
162 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
163 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
164 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
166 /* Default settings for DDR3 */
167 #ifndef CONFIG_TARGET_P2020RDB
168 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
169 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
170 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
171 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
172 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
173 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
175 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
176 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
177 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
178 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
180 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
181 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
182 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
183 #define CONFIG_SYS_DDR_RCW_1 0x00000000
184 #define CONFIG_SYS_DDR_RCW_2 0x00000000
185 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
186 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
187 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
188 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
190 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
191 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
192 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
193 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
194 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
195 #define CONFIG_SYS_DDR_MODE_1 0x40461520
196 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
197 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
203 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
204 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
205 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
206 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
208 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
209 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
210 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
211 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
212 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
213 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
214 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
218 * Local Bus Definitions
220 #if defined(CONFIG_TARGET_P1020RDB_PD)
221 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
222 #define CONFIG_SYS_FLASH_BASE 0xec000000
224 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
225 #define CONFIG_SYS_FLASH_BASE 0xef000000
228 #ifdef CONFIG_PHYS_64BIT
229 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
231 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
234 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
237 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
239 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
240 #define CONFIG_SYS_FLASH_QUIET_TEST
241 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
243 #undef CONFIG_SYS_FLASH_CHECKSUM
244 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
245 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
247 #define CONFIG_SYS_FLASH_EMPTY_INFO
250 #ifdef CONFIG_NAND_FSL_ELBC
251 #define CONFIG_SYS_NAND_BASE 0xff800000
252 #ifdef CONFIG_PHYS_64BIT
253 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
255 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
258 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
259 #define CONFIG_SYS_MAX_NAND_DEVICE 1
261 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
262 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
263 | BR_PS_8 /* Port Size = 8 bit */ \
264 | BR_MS_FCM /* MSEL = FCM */ \
266 #if defined(CONFIG_TARGET_P1020RDB_PD)
267 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
268 | OR_FCM_PGS /* Large Page*/ \
276 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
284 #endif /* CONFIG_NAND_FSL_ELBC */
286 #define CONFIG_SYS_INIT_RAM_LOCK
287 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
288 #ifdef CONFIG_PHYS_64BIT
289 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
290 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
291 /* The assembler doesn't like typecast */
292 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
293 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
294 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
296 /* Initial L1 address */
297 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
298 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
299 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
301 /* Size of used area in RAM */
302 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
304 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
305 GENERATED_GBL_DATA_SIZE)
306 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
308 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
310 #define CONFIG_SYS_CPLD_BASE 0xffa00000
311 #ifdef CONFIG_PHYS_64BIT
312 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
314 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
316 /* CPLD config size: 1Mb */
318 #define CONFIG_SYS_PMC_BASE 0xff980000
319 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
320 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
322 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
323 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
327 #ifdef CONFIG_VSC7385_ENET
328 #define __VSCFW_ADDR "vscfw_addr=ef000000\0"
329 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
331 #ifdef CONFIG_PHYS_64BIT
332 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
334 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
337 #define CONFIG_SYS_VSC7385_BR_PRELIM \
338 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
339 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
340 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
341 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
343 /* The size of the VSC7385 firmware image */
344 #define CONFIG_VSC7385_IMAGE_SIZE 8192
348 #define __VSCFW_ADDR ""
352 * Config the L2 Cache as L2 SRAM
354 #if defined(CONFIG_SPL_BUILD)
355 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
356 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
357 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
358 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
359 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
360 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
361 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
362 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
363 #if defined(CONFIG_TARGET_P2020RDB)
364 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
366 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
368 #elif defined(CONFIG_MTD_RAW_NAND)
369 #ifdef CONFIG_TPL_BUILD
370 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
371 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
372 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
373 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
374 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
375 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
376 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
377 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
379 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
380 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
381 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
382 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
383 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
384 #endif /* CONFIG_TPL_BUILD */
388 /* Serial Port - controlled on board with jumper J8
392 #undef CONFIG_SERIAL_SOFTWARE_FIFO
393 #define CONFIG_SYS_NS16550_SERIAL
394 #define CONFIG_SYS_NS16550_REG_SIZE 1
395 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
396 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
397 #define CONFIG_NS16550_MIN_FUNCTIONS
400 #define CONFIG_SYS_BAUDRATE_TABLE \
401 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
403 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
404 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
407 #if !CONFIG_IS_ENABLED(DM_I2C)
408 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
411 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
417 #define CONFIG_RTC_PT7C4338
418 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
419 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
421 /* enable read and write access to EEPROM */
423 #if defined(CONFIG_PCI)
426 * Memory space is mapped 1-1, but I/O space must start from 0.
429 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
430 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
431 #ifdef CONFIG_PHYS_64BIT
432 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
434 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
436 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
437 #ifdef CONFIG_PHYS_64BIT
438 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
440 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
443 /* controller 1, Slot 2, tgtid 1, Base address a000 */
444 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
445 #ifdef CONFIG_PHYS_64BIT
446 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
448 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
450 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
451 #ifdef CONFIG_PHYS_64BIT
452 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
454 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
457 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
458 #endif /* CONFIG_PCI */
460 #if defined(CONFIG_TSEC_ENET)
462 #define CONFIG_TSEC1_NAME "eTSEC1"
464 #define CONFIG_TSEC2_NAME "eTSEC2"
466 #define CONFIG_TSEC3_NAME "eTSEC3"
468 #define TSEC1_PHY_ADDR 2
469 #define TSEC2_PHY_ADDR 0
470 #define TSEC3_PHY_ADDR 1
472 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
473 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
474 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
476 #define TSEC1_PHYIDX 0
477 #define TSEC2_PHYIDX 0
478 #define TSEC3_PHYIDX 0
479 #endif /* CONFIG_TSEC_ENET */
484 #if defined(CONFIG_SDCARD)
485 #define CONFIG_FSL_FIXED_MMC_LOCATION
486 #elif defined(CONFIG_MTD_RAW_NAND)
487 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
488 #ifdef CONFIG_TPL_BUILD
489 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
491 #elif defined(CONFIG_SYS_RAMBOOT)
492 #define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
495 #define CONFIG_LOADS_ECHO /* echo on for serial download */
496 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
501 #define CONFIG_HAS_FSL_DR_USB
503 #if defined(CONFIG_HAS_FSL_DR_USB)
504 #ifdef CONFIG_USB_EHCI_HCD
505 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
509 #if defined(CONFIG_TARGET_P1020RDB_PD)
510 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
514 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
518 * Miscellaneous configurable options
522 * For booting Linux, the board info and command line data
523 * have to be in the first 64 MB of memory, since this is
524 * the maximum mapped by the Linux kernel during initialization.
526 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
527 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
530 * Environment Configuration
532 #define CONFIG_HOSTNAME "unknown"
533 #define CONFIG_ROOTPATH "/opt/nfsroot"
534 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
537 #define __NOR_RST_CMD \
538 norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NOR 1; \
539 i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
542 #define __SPI_RST_CMD \
543 spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SPI 1; \
544 i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
547 #define __SD_RST_CMD \
548 sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SD 1; \
549 i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
551 #ifdef __SW_BOOT_NAND
552 #define __NAND_RST_CMD \
553 nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NAND 1; \
554 i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
556 #ifdef __SW_BOOT_PCIE
557 #define __PCIE_RST_CMD \
558 pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_PCIE 1; \
559 i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
562 #define CONFIG_EXTRA_ENV_SETTINGS \
564 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
565 "loadaddr=1000000\0" \
566 "bootfile=uImage\0" \
567 "tftpflash=tftpboot $loadaddr $uboot; " \
568 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
569 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
570 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
571 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
572 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
573 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
574 "consoledev=ttyS0\0" \
575 "ramdiskaddr=2000000\0" \
576 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
577 "fdtaddr=1e00000\0" \
579 "jffs2nor=mtdblock3\0" \
580 "norbootaddr=ef080000\0" \
581 "norfdtaddr=ef040000\0" \
582 "jffs2nand=mtdblock9\0" \
583 "nandbootaddr=100000\0" \
584 "nandfdtaddr=80000\0" \
585 "ramdisk_size=120000\0" \
587 "map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 02 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 fd 1\0" \
588 "map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 00 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 fd 1\0" \
589 __stringify(__NOR_RST_CMD)"\0" \
590 __stringify(__SPI_RST_CMD)"\0" \
591 __stringify(__SD_RST_CMD)"\0" \
592 __stringify(__NAND_RST_CMD)"\0" \
593 __stringify(__PCIE_RST_CMD)"\0"
595 #define CONFIG_USB_FAT_BOOT \
596 "setenv bootargs root=/dev/ram rw " \
597 "console=$consoledev,$baudrate $othbootargs " \
598 "ramdisk_size=$ramdisk_size;" \
600 "fatload usb 0:2 $loadaddr $bootfile;" \
601 "fatload usb 0:2 $fdtaddr $fdtfile;" \
602 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
603 "bootm $loadaddr $ramdiskaddr $fdtaddr"
605 #define CONFIG_USB_EXT2_BOOT \
606 "setenv bootargs root=/dev/ram rw " \
607 "console=$consoledev,$baudrate $othbootargs " \
608 "ramdisk_size=$ramdisk_size;" \
610 "ext2load usb 0:4 $loadaddr $bootfile;" \
611 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
612 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
613 "bootm $loadaddr $ramdiskaddr $fdtaddr"
615 #define CONFIG_NORBOOT \
616 "setenv bootargs root=/dev/$jffs2nor rw " \
617 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
618 "bootm $norbootaddr - $norfdtaddr"
620 #endif /* __CONFIG_H */