2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
3 * Copyright (C) 2014 Bachmann electronic GmbH
5 * SPDX-License-Identifier: GPL-2.0+
11 #include "mx6_common.h"
13 /* Size of malloc() pool */
14 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
16 #define CONFIG_MISC_INIT_R
19 #define CONFIG_MXC_UART
20 #define CONFIG_MXC_UART_BASE UART1_BASE
24 #define CONFIG_MXC_SPI
25 #define CONFIG_SF_DEFAULT_BUS 2
26 #define CONFIG_SF_DEFAULT_CS 0
27 #define CONFIG_SF_DEFAULT_SPEED 25000000
28 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
31 #define CONFIG_PCA953X
32 #define CONFIG_SYS_I2C_PCA953X_ADDR 0x20
33 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} }
34 #define CONFIG_CMD_PCA953X
35 #define CONFIG_CMD_PCA953X_INFO
38 #define CONFIG_SYS_I2C
39 #define CONFIG_SYS_I2C_MXC
40 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
41 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
42 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
43 #define CONFIG_SYS_I2C_SPEED 100000
46 #define CONFIG_CMD_IMXOTP
47 #define CONFIG_IMX_OTP
48 #define IMX_OTP_BASE OCOTP_BASE_ADDR
49 #define IMX_OTP_ADDR_MAX 0x7F
50 #define IMX_OTP_DATA_ERROR_VAL 0xBADABADA
51 #define IMX_OTPWRITE_ENABLED
54 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
55 #define CONFIG_SYS_FSL_USDHC_NUM 2
58 #define CONFIG_USB_EHCI
59 #define CONFIG_USB_EHCI_MX6
60 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
61 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
64 #define CONFIG_CMD_SATA
70 #ifdef CONFIG_CMD_SATA
71 #define CONFIG_DWC_AHSATA
72 #define CONFIG_SYS_SATA_MAX_DEVICE 1
73 #define CONFIG_DWC_AHSATA_PORT_ID 0
74 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
82 #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
83 #define CONFIG_SPL_SPI_LOAD
86 #define CONFIG_FEC_MXC
88 #define IMX_FEC_BASE ENET_BASE_ADDR
89 #define CONFIG_FEC_XCV_TYPE MII100
90 #define CONFIG_ETHPRIME "FEC"
91 #define CONFIG_FEC_MXC_PHYADDR 0x5
93 #define CONFIG_PHY_SMSC
96 #define CONFIG_CMD_EEPROM
97 #define CONFIG_ENV_EEPROM_IS_ON_I2C
98 #define CONFIG_SYS_I2C_EEPROM_BUS 1
99 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
100 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
101 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
104 #define CONFIG_PREBOOT ""
106 /* Print Buffer Size */
107 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
109 /* Physical Memory Map */
110 #define CONFIG_NR_DRAM_BANKS 1
111 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
113 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
114 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
115 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
117 #define CONFIG_SYS_INIT_SP_OFFSET \
118 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
119 #define CONFIG_SYS_INIT_SP_ADDR \
120 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
122 /* Environment organization */
123 #define CONFIG_ENV_IS_IN_SPI_FLASH
124 #define CONFIG_ENV_SIZE (64 * 1024) /* 64 kb */
125 #define CONFIG_ENV_OFFSET (1024 * 1024)
126 /* M25P16 has an erase size of 64 KiB */
127 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
128 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
129 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
130 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
131 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
133 #define CONFIG_BOOTP_SERVERIP
134 #define CONFIG_BOOTP_BOOTFILE
136 #endif /* __CONFIG_H */