include/configs/omapl138_lcdk.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   4  *
   5  * Based on davinci_dvevm.h. Original Copyrights follow:
   6  *
   7  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * Board
  15  */
  16
  17 /*
  18  * SoC Configuration
  19  */
  20 #ifndef __ASSEMBLY__
  21 unsigned long get_board_sys_clk(void);
  22 #endif
  23 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  24 #define CONFIG_SYS_OSCIN_FREQ           24000000
  25 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
  26 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
  27
  28 /*
  29  * Memory Info
  30  */
  31 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  32 #define PHYS_SDRAM_1_SIZE       (128 << 20) /* SDRAM size 128MB */
  33 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  34
  35 #define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
  36 #define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
  37
  38 /* memtest start addr */
  39
  40 /* memtest will be run on 16MB */
  41
  42 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
  43         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
  44         DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
  45         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
  46         DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
  47         DAVINCI_SYSCFG_SUSPSRC_I2C)
  48
  49 /*
  50  * PLL configuration
  51  */
  52
  53 /* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
  54 #define CONFIG_SYS_DA850_PLL0_PLLM     18
  55 #define CONFIG_SYS_DA850_PLL1_PLLM     21
  56
  57 /*
  58  * DDR2 memory configuration
  59  */
  60 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  61                                         DV_DDR_PHY_EXT_STRBEN | \
  62                                         (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  63
  64 #define CONFIG_SYS_DA850_DDR2_SDBCR (             \
  65         (1 << DV_DDR_SDCR_DDR2EN_SHIFT)         | \
  66         (1 << DV_DDR_SDCR_DDREN_SHIFT)          | \
  67         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT)        | \
  68         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)      | \
  69         (4 << DV_DDR_SDCR_CL_SHIFT)             | \
  70         (3 << DV_DDR_SDCR_IBANK_SHIFT)          | \
  71         (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  72
  73 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
  74 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
  75
  76 #define CONFIG_SYS_DA850_DDR2_SDTIMR (            \
  77         (19 << DV_DDR_SDTMR1_RFC_SHIFT)         | \
  78         (1 << DV_DDR_SDTMR1_RP_SHIFT)           | \
  79         (1 << DV_DDR_SDTMR1_RCD_SHIFT)          | \
  80         (2 << DV_DDR_SDTMR1_WR_SHIFT)           | \
  81         (6 << DV_DDR_SDTMR1_RAS_SHIFT)          | \
  82         (8 << DV_DDR_SDTMR1_RC_SHIFT)           | \
  83         (1 << DV_DDR_SDTMR1_RRD_SHIFT)          | \
  84         (1 << DV_DDR_SDTMR1_WTR_SHIFT))
  85
  86 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (           \
  87         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT)       | \
  88         (2 << DV_DDR_SDTMR2_XP_SHIFT)           | \
  89         (0 << DV_DDR_SDTMR2_ODT_SHIFT)          | \
  90         (20 << DV_DDR_SDTMR2_XSNR_SHIFT)        | \
  91         (199 << DV_DDR_SDTMR2_XSRD_SHIFT)       | \
  92         (1 << DV_DDR_SDTMR2_RTP_SHIFT)          | \
  93         (2 << DV_DDR_SDTMR2_CKE_SHIFT))
  94
  95 #define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000492
  96 #define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
  97
  98 /*
  99  * Serial Driver info
 100  */
 101 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
 102
 103 #define CONFIG_SYS_SPI_BASE             DAVINCI_SPI1_BASE
 104 #define CONFIG_SYS_SPI_CLK              clk_get(DAVINCI_SPI1_CLKID)
 105
 106 /*
 107  * I2C Configuration
 108  */
 109 #define CONFIG_SYS_DAVINCI_I2C_SPEED    25000
 110 #define CONFIG_SYS_DAVINCI_I2C_SLAVE    10 /* Bogus, master-only in U-Boot */
 111 #define CONFIG_SYS_I2C_EXPANDER_ADDR    0x20
 112
 113 /*
 114  * Flash & Environment
 115  */
 116 #ifdef CONFIG_MTD_RAW_NAND
 117 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 118 #define CONFIG_SYS_NAND_PAGE_2K
 119 #define CONFIG_SYS_NAND_CS              3
 120 #define CONFIG_SYS_NAND_BASE            DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
 121 #define CONFIG_SYS_NAND_MASK_CLE        0x10
 122 #define CONFIG_SYS_NAND_MASK_ALE        0x8
 123 #undef CONFIG_SYS_NAND_HW_ECC
 124 #define CONFIG_SYS_MAX_NAND_DEVICE      1 /* Max number of NAND devices */
 125 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 126 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
 127 #define CONFIG_SYS_NAND_U_BOOT_SIZE     SZ_512K
 128 #define CONFIG_SYS_NAND_U_BOOT_DST      0xc1080000
 129 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 130 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
 131                                         CONFIG_SYS_NAND_U_BOOT_SIZE - \
 132                                         CONFIG_SYS_MALLOC_LEN -       \
 133                                         GENERATED_GBL_DATA_SIZE)
 134 #define CONFIG_SYS_NAND_ECCPOS          {                               \
 135                                 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,     \
 136                                 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
 137                                 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
 138                                 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
 139 #define CONFIG_SYS_NAND_ECCSIZE         512
 140 #define CONFIG_SYS_NAND_ECCBYTES        10
 141 #endif
 142
 143 /*
 144  * Network & Ethernet Configuration
 145  */
 146 #ifdef CONFIG_DRIVER_TI_EMAC
 147 #define CONFIG_NET_RETRY_COUNT  10
 148 #endif
 149
 150 /*
 151  * U-Boot general configuration
 152  */
 153 #define CONFIG_BOOTFILE         "zImage" /* Boot file name */
 154 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 155 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 156
 157 /*
 158  * USB Configs
 159  */
 160 #define CONFIG_USB_OHCI_NEW
 161 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 162
 163 /*
 164  * Linux Information
 165  */
 166 #define LINUX_BOOT_PARAM_ADDR   (PHYS_SDRAM_1 + 0x100)
 167
 168 #define DEFAULT_LINUX_BOOT_ENV \
 169         "loadaddr=0xc0700000\0" \
 170         "fdtaddr=0xc0600000\0" \
 171         "scriptaddr=0xc0600000\0"
 172
 173 #include <environment/ti/mmc.h>
 174
 175 #define CONFIG_EXTRA_ENV_SETTINGS \
 176         DEFAULT_LINUX_BOOT_ENV \
 177         DEFAULT_MMC_TI_ARGS \
 178         "bootpart=0:2\0" \
 179         "bootdir=/boot\0" \
 180         "bootfile=zImage\0" \
 181         "fdtfile=da850-lcdk.dtb\0" \
 182         "boot_fdt=yes\0" \
 183         "boot_fit=0\0" \
 184         "console=ttyS2,115200n8\0"
 185
 186 #ifdef CONFIG_CMD_BDI
 187 #define CONFIG_CLOCKS
 188 #endif
 189
 190 /* SD/MMC */
 191
 192 /* defines for SPL */
 193 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE - \
 194                                                 CONFIG_SYS_MALLOC_LEN)
 195 #define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
 196 #define CONFIG_SPL_STACK        0x8001ff00
 197 #define CONFIG_SPL_MAX_FOOTPRINT        32768
 198 #define CONFIG_SPL_PAD_TO       32768
 199
 200 /* additions for new relocation code, must added to all boards */
 201 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
 202 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
 203                                         GENERATED_GBL_DATA_SIZE)
 204
 205 #include <asm/arch/hardware.h>
 206
 207 #endif /* __CONFIG_H */