1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Based on davinci_dvevm.h. Original Copyrights follow:
7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
20 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
21 #define CONFIG_SYS_OSCIN_FREQ 24000000
22 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
23 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
24 #define CONFIG_SYS_HZ 1000
29 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
30 #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
31 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
33 #define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
34 #define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
36 /* memtest start addr */
38 /* memtest will be run on 16MB */
40 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
41 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
42 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
43 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
44 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
45 DAVINCI_SYSCFG_SUSPSRC_I2C)
51 /* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
52 #define CONFIG_SYS_DA850_PLL0_PLLM 18
53 #define CONFIG_SYS_DA850_PLL1_PLLM 21
56 * DDR2 memory configuration
58 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
59 DV_DDR_PHY_EXT_STRBEN | \
60 (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
62 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \
63 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
64 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
65 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
66 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
67 (4 << DV_DDR_SDCR_CL_SHIFT) | \
68 (3 << DV_DDR_SDCR_IBANK_SHIFT) | \
69 (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
71 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
72 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
74 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
75 (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \
76 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
77 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
78 (2 << DV_DDR_SDTMR1_WR_SHIFT) | \
79 (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \
80 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
81 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
82 (1 << DV_DDR_SDTMR1_WTR_SHIFT))
84 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
85 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
86 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
87 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
88 (20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
89 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
90 (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
91 (2 << DV_DDR_SDTMR2_CKE_SHIFT))
93 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492
94 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
99 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
101 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
102 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
107 #define CONFIG_SYS_DAVINCI_I2C_SPEED 25000
108 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
109 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
112 * Flash & Environment
114 #ifdef CONFIG_MTD_RAW_NAND
115 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
116 #define CONFIG_SYS_NAND_PAGE_2K
117 #define CONFIG_SYS_NAND_CS 3
118 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
119 #define CONFIG_SYS_NAND_MASK_CLE 0x10
120 #define CONFIG_SYS_NAND_MASK_ALE 0x8
121 #undef CONFIG_SYS_NAND_HW_ECC
122 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
123 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
124 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
125 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
126 #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
127 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
128 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
129 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
130 CONFIG_SYS_NAND_U_BOOT_SIZE - \
131 CONFIG_SYS_MALLOC_LEN - \
132 GENERATED_GBL_DATA_SIZE)
133 #define CONFIG_SYS_NAND_ECCPOS { \
134 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
135 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
136 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
137 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
138 #define CONFIG_SYS_NAND_ECCSIZE 512
139 #define CONFIG_SYS_NAND_ECCBYTES 10
143 * Network & Ethernet Configuration
145 #ifdef CONFIG_DRIVER_TI_EMAC
146 #define CONFIG_NET_RETRY_COUNT 10
150 * U-Boot general configuration
152 #define CONFIG_BOOTFILE "zImage" /* Boot file name */
153 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
154 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
159 #define CONFIG_USB_OHCI_NEW
160 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
165 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
166 #define CONFIG_BOOTCOMMAND \
170 #define DEFAULT_LINUX_BOOT_ENV \
171 "loadaddr=0xc0700000\0" \
172 "fdtaddr=0xc0600000\0" \
173 "scriptaddr=0xc0600000\0"
175 #include <environment/ti/mmc.h>
177 #define CONFIG_EXTRA_ENV_SETTINGS \
178 DEFAULT_LINUX_BOOT_ENV \
179 DEFAULT_MMC_TI_ARGS \
182 "bootfile=zImage\0" \
183 "fdtfile=da850-lcdk.dtb\0" \
186 "console=ttyS2,115200n8\0"
188 #ifdef CONFIG_CMD_BDI
189 #define CONFIG_CLOCKS
194 /* defines for SPL */
195 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
196 CONFIG_SYS_MALLOC_LEN)
197 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
198 #define CONFIG_SPL_STACK 0x8001ff00
199 #define CONFIG_SPL_MAX_FOOTPRINT 32768
200 #define CONFIG_SPL_PAD_TO 32768
202 /* additions for new relocation code, must added to all boards */
203 #define CONFIG_SYS_SDRAM_BASE 0xc0000000
204 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
205 GENERATED_GBL_DATA_SIZE)
207 #include <asm/arch/hardware.h>
209 #endif /* __CONFIG_H */