1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Based on davinci_dvevm.h. Original Copyrights follow:
7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
20 #define CFG_SYS_OSCIN_FREQ 24000000
21 #define CFG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
22 #define CFG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
27 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
28 #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
29 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
31 /* memtest start addr */
33 /* memtest will be run on 16MB */
35 #define CFG_SYS_DA850_SYSCFG_SUSPSRC ( \
36 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
37 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
38 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
39 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
40 DAVINCI_SYSCFG_SUSPSRC_I2C)
46 /* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
47 #define CFG_SYS_DA850_PLL0_PLLM 18
48 #define CFG_SYS_DA850_PLL1_PLLM 21
51 * DDR2 memory configuration
53 #define CFG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
54 DV_DDR_PHY_EXT_STRBEN | \
55 (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
57 #define CFG_SYS_DA850_DDR2_SDBCR ( \
58 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
59 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
60 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
61 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
62 (4 << DV_DDR_SDCR_CL_SHIFT) | \
63 (3 << DV_DDR_SDCR_IBANK_SHIFT) | \
64 (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
66 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
67 #define CFG_SYS_DA850_DDR2_SDBCR2 0
69 #define CFG_SYS_DA850_DDR2_SDTIMR ( \
70 (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \
71 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
72 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
73 (2 << DV_DDR_SDTMR1_WR_SHIFT) | \
74 (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \
75 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
76 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
77 (1 << DV_DDR_SDTMR1_WTR_SHIFT))
79 #define CFG_SYS_DA850_DDR2_SDTIMR2 ( \
80 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
81 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
82 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
83 (20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
84 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
85 (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
86 (2 << DV_DDR_SDTMR2_CKE_SHIFT))
88 #define CFG_SYS_DA850_DDR2_SDRCR 0x00000492
89 #define CFG_SYS_DA850_DDR2_PBBPR 0x30
94 #define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
96 #define CFG_SYS_SPI_BASE DAVINCI_SPI1_BASE
97 #define CFG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
102 #define CFG_SYS_I2C_EXPANDER_ADDR 0x20
105 * Flash & Environment
107 #ifdef CONFIG_MTD_RAW_NAND
108 #define CFG_SYS_NAND_CS 3
109 #define CFG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
110 #define CFG_SYS_NAND_MASK_CLE 0x10
111 #define CFG_SYS_NAND_MASK_ALE 0x8
112 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
113 #define CFG_SYS_NAND_U_BOOT_SIZE SZ_512K
114 #define CFG_SYS_NAND_U_BOOT_DST 0xc1080000
115 #define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST
116 #define CFG_SYS_NAND_ECCPOS { \
117 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
118 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
119 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
120 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
121 #define CFG_SYS_NAND_ECCSIZE 512
122 #define CFG_SYS_NAND_ECCBYTES 10
126 * U-Boot general configuration
132 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
134 #define DEFAULT_LINUX_BOOT_ENV \
135 "loadaddr=0xc0700000\0" \
136 "fdtaddr=0xc0600000\0" \
137 "scriptaddr=0xc0600000\0"
139 #include <environment/ti/mmc.h>
141 #define CONFIG_EXTRA_ENV_SETTINGS \
142 DEFAULT_LINUX_BOOT_ENV \
143 DEFAULT_MMC_TI_ARGS \
146 "bootfile=zImage\0" \
147 "fdtfile=da850-lcdk.dtb\0" \
150 "console=ttyS2,115200n8\0"
154 /* defines for SPL */
156 /* additions for new relocation code, must added to all boards */
157 #define CFG_SYS_SDRAM_BASE 0xc0000000
159 #include <asm/arch/hardware.h>
161 #endif /* __CONFIG_H */