include/configs/omapl138_lcdk.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   4  *
   5  * Based on davinci_dvevm.h. Original Copyrights follow:
   6  *
   7  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * Board
  15  */
  16
  17 /*
  18  * SoC Configuration
  19  */
  20 #define CONFIG_SYS_OSCIN_FREQ           24000000
  21 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
  22 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
  23
  24 /*
  25  * Memory Info
  26  */
  27 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  28 #define PHYS_SDRAM_1_SIZE       (128 << 20) /* SDRAM size 128MB */
  29 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  30
  31 /* memtest start addr */
  32
  33 /* memtest will be run on 16MB */
  34
  35 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
  36         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
  37         DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
  38         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
  39         DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
  40         DAVINCI_SYSCFG_SUSPSRC_I2C)
  41
  42 /*
  43  * PLL configuration
  44  */
  45
  46 /* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
  47 #define CONFIG_SYS_DA850_PLL0_PLLM     18
  48 #define CONFIG_SYS_DA850_PLL1_PLLM     21
  49
  50 /*
  51  * DDR2 memory configuration
  52  */
  53 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  54                                         DV_DDR_PHY_EXT_STRBEN | \
  55                                         (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  56
  57 #define CONFIG_SYS_DA850_DDR2_SDBCR (             \
  58         (1 << DV_DDR_SDCR_DDR2EN_SHIFT)         | \
  59         (1 << DV_DDR_SDCR_DDREN_SHIFT)          | \
  60         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT)        | \
  61         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)      | \
  62         (4 << DV_DDR_SDCR_CL_SHIFT)             | \
  63         (3 << DV_DDR_SDCR_IBANK_SHIFT)          | \
  64         (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  65
  66 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
  67 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
  68
  69 #define CONFIG_SYS_DA850_DDR2_SDTIMR (            \
  70         (19 << DV_DDR_SDTMR1_RFC_SHIFT)         | \
  71         (1 << DV_DDR_SDTMR1_RP_SHIFT)           | \
  72         (1 << DV_DDR_SDTMR1_RCD_SHIFT)          | \
  73         (2 << DV_DDR_SDTMR1_WR_SHIFT)           | \
  74         (6 << DV_DDR_SDTMR1_RAS_SHIFT)          | \
  75         (8 << DV_DDR_SDTMR1_RC_SHIFT)           | \
  76         (1 << DV_DDR_SDTMR1_RRD_SHIFT)          | \
  77         (1 << DV_DDR_SDTMR1_WTR_SHIFT))
  78
  79 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (           \
  80         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT)       | \
  81         (2 << DV_DDR_SDTMR2_XP_SHIFT)           | \
  82         (0 << DV_DDR_SDTMR2_ODT_SHIFT)          | \
  83         (20 << DV_DDR_SDTMR2_XSNR_SHIFT)        | \
  84         (199 << DV_DDR_SDTMR2_XSRD_SHIFT)       | \
  85         (1 << DV_DDR_SDTMR2_RTP_SHIFT)          | \
  86         (2 << DV_DDR_SDTMR2_CKE_SHIFT))
  87
  88 #define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000492
  89 #define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
  90
  91 /*
  92  * Serial Driver info
  93  */
  94 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
  95
  96 #define CONFIG_SYS_SPI_BASE             DAVINCI_SPI1_BASE
  97 #define CONFIG_SYS_SPI_CLK              clk_get(DAVINCI_SPI1_CLKID)
  98
  99 /*
 100  * I2C Configuration
 101  */
 102 #define CONFIG_SYS_I2C_EXPANDER_ADDR    0x20
 103
 104 /*
 105  * Flash & Environment
 106  */
 107 #ifdef CONFIG_MTD_RAW_NAND
 108 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 109 #define CONFIG_SYS_NAND_PAGE_2K
 110 #define CONFIG_SYS_NAND_CS              3
 111 #define CONFIG_SYS_NAND_BASE            DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
 112 #define CONFIG_SYS_NAND_MASK_CLE        0x10
 113 #define CONFIG_SYS_NAND_MASK_ALE        0x8
 114 #undef CONFIG_SYS_NAND_HW_ECC
 115 #define CONFIG_SYS_MAX_NAND_DEVICE      1 /* Max number of NAND devices */
 116 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 117 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
 118 #define CONFIG_SYS_NAND_U_BOOT_SIZE     SZ_512K
 119 #define CONFIG_SYS_NAND_U_BOOT_DST      0xc1080000
 120 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 121 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
 122                                         CONFIG_SYS_NAND_U_BOOT_SIZE - \
 123                                         CONFIG_SYS_MALLOC_LEN -       \
 124                                         GENERATED_GBL_DATA_SIZE)
 125 #define CONFIG_SYS_NAND_ECCPOS          {                               \
 126                                 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,     \
 127                                 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
 128                                 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
 129                                 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
 130 #define CONFIG_SYS_NAND_ECCSIZE         512
 131 #define CONFIG_SYS_NAND_ECCBYTES        10
 132 #endif
 133
 134 /*
 135  * U-Boot general configuration
 136  */
 137
 138 /*
 139  * Linux Information
 140  */
 141 #define LINUX_BOOT_PARAM_ADDR   (PHYS_SDRAM_1 + 0x100)
 142
 143 #define DEFAULT_LINUX_BOOT_ENV \
 144         "loadaddr=0xc0700000\0" \
 145         "fdtaddr=0xc0600000\0" \
 146         "scriptaddr=0xc0600000\0"
 147
 148 #include <environment/ti/mmc.h>
 149
 150 #define CONFIG_EXTRA_ENV_SETTINGS \
 151         DEFAULT_LINUX_BOOT_ENV \
 152         DEFAULT_MMC_TI_ARGS \
 153         "bootpart=0:2\0" \
 154         "bootdir=/boot\0" \
 155         "bootfile=zImage\0" \
 156         "fdtfile=da850-lcdk.dtb\0" \
 157         "boot_fdt=yes\0" \
 158         "boot_fit=0\0" \
 159         "console=ttyS2,115200n8\0"
 160
 161 /* SD/MMC */
 162
 163 /* defines for SPL */
 164
 165 /* additions for new relocation code, must added to all boards */
 166 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
 167
 168 #include <asm/arch/hardware.h>
 169
 170 #endif /* __CONFIG_H */