include/configs/omapl138_lcdk.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   4  *
   5  * Based on davinci_dvevm.h. Original Copyrights follow:
   6  *
   7  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * Board
  15  */
  16
  17 /*
  18  * SoC Configuration
  19  */
  20 #define CONFIG_SYS_CLK_FREQ             clk_get(DAVINCI_ARM_CLKID)
  21 #define CONFIG_SYS_OSCIN_FREQ           24000000
  22 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
  23 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
  24
  25 /*
  26  * Memory Info
  27  */
  28 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  29 #define PHYS_SDRAM_1_SIZE       (128 << 20) /* SDRAM size 128MB */
  30 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  31
  32 #define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
  33 #define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
  34
  35 /* memtest start addr */
  36
  37 /* memtest will be run on 16MB */
  38
  39 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
  40         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
  41         DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
  42         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
  43         DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
  44         DAVINCI_SYSCFG_SUSPSRC_I2C)
  45
  46 /*
  47  * PLL configuration
  48  */
  49
  50 /* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
  51 #define CONFIG_SYS_DA850_PLL0_PLLM     18
  52 #define CONFIG_SYS_DA850_PLL1_PLLM     21
  53
  54 /*
  55  * DDR2 memory configuration
  56  */
  57 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  58                                         DV_DDR_PHY_EXT_STRBEN | \
  59                                         (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  60
  61 #define CONFIG_SYS_DA850_DDR2_SDBCR (             \
  62         (1 << DV_DDR_SDCR_DDR2EN_SHIFT)         | \
  63         (1 << DV_DDR_SDCR_DDREN_SHIFT)          | \
  64         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT)        | \
  65         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)      | \
  66         (4 << DV_DDR_SDCR_CL_SHIFT)             | \
  67         (3 << DV_DDR_SDCR_IBANK_SHIFT)          | \
  68         (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  69
  70 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
  71 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
  72
  73 #define CONFIG_SYS_DA850_DDR2_SDTIMR (            \
  74         (19 << DV_DDR_SDTMR1_RFC_SHIFT)         | \
  75         (1 << DV_DDR_SDTMR1_RP_SHIFT)           | \
  76         (1 << DV_DDR_SDTMR1_RCD_SHIFT)          | \
  77         (2 << DV_DDR_SDTMR1_WR_SHIFT)           | \
  78         (6 << DV_DDR_SDTMR1_RAS_SHIFT)          | \
  79         (8 << DV_DDR_SDTMR1_RC_SHIFT)           | \
  80         (1 << DV_DDR_SDTMR1_RRD_SHIFT)          | \
  81         (1 << DV_DDR_SDTMR1_WTR_SHIFT))
  82
  83 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (           \
  84         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT)       | \
  85         (2 << DV_DDR_SDTMR2_XP_SHIFT)           | \
  86         (0 << DV_DDR_SDTMR2_ODT_SHIFT)          | \
  87         (20 << DV_DDR_SDTMR2_XSNR_SHIFT)        | \
  88         (199 << DV_DDR_SDTMR2_XSRD_SHIFT)       | \
  89         (1 << DV_DDR_SDTMR2_RTP_SHIFT)          | \
  90         (2 << DV_DDR_SDTMR2_CKE_SHIFT))
  91
  92 #define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000492
  93 #define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
  94
  95 /*
  96  * Serial Driver info
  97  */
  98 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
  99
 100 #define CONFIG_SYS_SPI_BASE             DAVINCI_SPI1_BASE
 101 #define CONFIG_SYS_SPI_CLK              clk_get(DAVINCI_SPI1_CLKID)
 102
 103 /*
 104  * I2C Configuration
 105  */
 106 #define CONFIG_SYS_DAVINCI_I2C_SPEED    25000
 107 #define CONFIG_SYS_DAVINCI_I2C_SLAVE    10 /* Bogus, master-only in U-Boot */
 108 #define CONFIG_SYS_I2C_EXPANDER_ADDR    0x20
 109
 110 /*
 111  * Flash & Environment
 112  */
 113 #ifdef CONFIG_MTD_RAW_NAND
 114 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 115 #define CONFIG_SYS_NAND_PAGE_2K
 116 #define CONFIG_SYS_NAND_CS              3
 117 #define CONFIG_SYS_NAND_BASE            DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
 118 #define CONFIG_SYS_NAND_MASK_CLE        0x10
 119 #define CONFIG_SYS_NAND_MASK_ALE        0x8
 120 #undef CONFIG_SYS_NAND_HW_ECC
 121 #define CONFIG_SYS_MAX_NAND_DEVICE      1 /* Max number of NAND devices */
 122 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 123 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
 124 #define CONFIG_SYS_NAND_U_BOOT_SIZE     SZ_512K
 125 #define CONFIG_SYS_NAND_U_BOOT_DST      0xc1080000
 126 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 127 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
 128                                         CONFIG_SYS_NAND_U_BOOT_SIZE - \
 129                                         CONFIG_SYS_MALLOC_LEN -       \
 130                                         GENERATED_GBL_DATA_SIZE)
 131 #define CONFIG_SYS_NAND_ECCPOS          {                               \
 132                                 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,     \
 133                                 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
 134                                 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
 135                                 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
 136 #define CONFIG_SYS_NAND_ECCSIZE         512
 137 #define CONFIG_SYS_NAND_ECCBYTES        10
 138 #endif
 139
 140 /*
 141  * Network & Ethernet Configuration
 142  */
 143 #ifdef CONFIG_DRIVER_TI_EMAC
 144 #define CONFIG_NET_RETRY_COUNT  10
 145 #endif
 146
 147 /*
 148  * U-Boot general configuration
 149  */
 150 #define CONFIG_BOOTFILE         "zImage" /* Boot file name */
 151 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 152 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 153
 154 /*
 155  * USB Configs
 156  */
 157 #define CONFIG_USB_OHCI_NEW
 158 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 159
 160 /*
 161  * Linux Information
 162  */
 163 #define LINUX_BOOT_PARAM_ADDR   (PHYS_SDRAM_1 + 0x100)
 164
 165 #define DEFAULT_LINUX_BOOT_ENV \
 166         "loadaddr=0xc0700000\0" \
 167         "fdtaddr=0xc0600000\0" \
 168         "scriptaddr=0xc0600000\0"
 169
 170 #include <environment/ti/mmc.h>
 171
 172 #define CONFIG_EXTRA_ENV_SETTINGS \
 173         DEFAULT_LINUX_BOOT_ENV \
 174         DEFAULT_MMC_TI_ARGS \
 175         "bootpart=0:2\0" \
 176         "bootdir=/boot\0" \
 177         "bootfile=zImage\0" \
 178         "fdtfile=da850-lcdk.dtb\0" \
 179         "boot_fdt=yes\0" \
 180         "boot_fit=0\0" \
 181         "console=ttyS2,115200n8\0"
 182
 183 #ifdef CONFIG_CMD_BDI
 184 #define CONFIG_CLOCKS
 185 #endif
 186
 187 /* SD/MMC */
 188
 189 /* defines for SPL */
 190 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE - \
 191                                                 CONFIG_SYS_MALLOC_LEN)
 192 #define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
 193 #define CONFIG_SPL_STACK        0x8001ff00
 194 #define CONFIG_SPL_MAX_FOOTPRINT        32768
 195 #define CONFIG_SPL_PAD_TO       32768
 196
 197 /* additions for new relocation code, must added to all boards */
 198 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
 199 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
 200                                         GENERATED_GBL_DATA_SIZE)
 201
 202 #include <asm/arch/hardware.h>
 203
 204 #endif /* __CONFIG_H */