include/configs/omapl138_lcdk.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   4  *
   5  * Based on davinci_dvevm.h. Original Copyrights follow:
   6  *
   7  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * Board
  15  */
  16 #define CONFIG_DRIVER_TI_EMAC
  17 #undef CONFIG_USE_SPIFLASH
  18 #undef  CONFIG_SYS_USE_NOR
  19
  20 /*
  21 * Disable DM_* for SPL build and can be re-enabled after adding
  22 * DM support in SPL
  23 */
  24 #ifdef CONFIG_SPL_BUILD
  25 #undef CONFIG_DM_I2C
  26 #undef CONFIG_DM_I2C_COMPAT
  27 #endif
  28 /*
  29  * SoC Configuration
  30  */
  31 #define CONFIG_MACH_OMAPL138_LCDK
  32 #define CONFIG_SYS_CLK_FREQ             clk_get(DAVINCI_ARM_CLKID)
  33 #define CONFIG_SYS_OSCIN_FREQ           24000000
  34 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
  35 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
  36 #define CONFIG_SYS_HZ                   1000
  37 #define CONFIG_SKIP_LOWLEVEL_INIT
  38
  39 /*
  40  * Memory Info
  41  */
  42 #define CONFIG_SYS_MALLOC_LEN   (0x10000 + 1*1024*1024) /* malloc() len */
  43 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  44 #define PHYS_SDRAM_1_SIZE       (128 << 20) /* SDRAM size 128MB */
  45 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  46
  47 /* memtest start addr */
  48 #define CONFIG_SYS_MEMTEST_START        (PHYS_SDRAM_1 + 0x2000000)
  49
  50 /* memtest will be run on 16MB */
  51 #define CONFIG_SYS_MEMTEST_END  (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
  52
  53 #define CONFIG_NR_DRAM_BANKS    1 /* we have 1 bank of DRAM */
  54
  55 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
  56         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
  57         DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
  58         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
  59         DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
  60         DAVINCI_SYSCFG_SUSPSRC_I2C)
  61
  62 /*
  63  * PLL configuration
  64  */
  65
  66 /* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
  67 #define CONFIG_SYS_DA850_PLL0_PLLM     18
  68 #define CONFIG_SYS_DA850_PLL1_PLLM     21
  69
  70 /*
  71  * DDR2 memory configuration
  72  */
  73 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  74                                         DV_DDR_PHY_EXT_STRBEN | \
  75                                         (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  76
  77 #define CONFIG_SYS_DA850_DDR2_SDBCR (             \
  78         (1 << DV_DDR_SDCR_DDR2EN_SHIFT)         | \
  79         (1 << DV_DDR_SDCR_DDREN_SHIFT)          | \
  80         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT)        | \
  81         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)      | \
  82         (4 << DV_DDR_SDCR_CL_SHIFT)             | \
  83         (3 << DV_DDR_SDCR_IBANK_SHIFT)          | \
  84         (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  85
  86 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
  87 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
  88
  89 #define CONFIG_SYS_DA850_DDR2_SDTIMR (            \
  90         (19 << DV_DDR_SDTMR1_RFC_SHIFT)         | \
  91         (1 << DV_DDR_SDTMR1_RP_SHIFT)           | \
  92         (1 << DV_DDR_SDTMR1_RCD_SHIFT)          | \
  93         (2 << DV_DDR_SDTMR1_WR_SHIFT)           | \
  94         (6 << DV_DDR_SDTMR1_RAS_SHIFT)          | \
  95         (8 << DV_DDR_SDTMR1_RC_SHIFT)           | \
  96         (1 << DV_DDR_SDTMR1_RRD_SHIFT)          | \
  97         (1 << DV_DDR_SDTMR1_WTR_SHIFT))
  98
  99 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (           \
 100         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT)       | \
 101         (2 << DV_DDR_SDTMR2_XP_SHIFT)           | \
 102         (0 << DV_DDR_SDTMR2_ODT_SHIFT)          | \
 103         (20 << DV_DDR_SDTMR2_XSNR_SHIFT)        | \
 104         (199 << DV_DDR_SDTMR2_XSRD_SHIFT)       | \
 105         (1 << DV_DDR_SDTMR2_RTP_SHIFT)          | \
 106         (2 << DV_DDR_SDTMR2_CKE_SHIFT))
 107
 108 #define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000492
 109 #define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
 110
 111 /*
 112  * Serial Driver info
 113  */
 114 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
 115 #if !defined(CONFIG_DM_SERIAL)
 116 #define CONFIG_SYS_NS16550_SERIAL
 117 #define CONFIG_SYS_NS16550_REG_SIZE     -4      /* NS16550 register size */
 118 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
 119 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
 120 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 121 #endif
 122
 123 #define CONFIG_SYS_SPI_BASE             DAVINCI_SPI1_BASE
 124 #define CONFIG_SYS_SPI_CLK              clk_get(DAVINCI_SPI1_CLKID)
 125 #define CONFIG_SF_DEFAULT_SPEED         30000000
 126 #define CONFIG_ENV_SPI_MAX_HZ   CONFIG_SF_DEFAULT_SPEED
 127
 128 #ifdef CONFIG_USE_SPIFLASH
 129 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x8000
 130 #define CONFIG_SYS_SPI_U_BOOT_SIZE      0x30000
 131 #endif
 132
 133 /*
 134  * I2C Configuration
 135  */
 136 #define CONFIG_SYS_I2C_DAVINCI
 137 #define CONFIG_SYS_DAVINCI_I2C_SPEED    25000
 138 #define CONFIG_SYS_DAVINCI_I2C_SLAVE    10 /* Bogus, master-only in U-Boot */
 139 #define CONFIG_SYS_I2C_EXPANDER_ADDR    0x20
 140
 141 /*
 142  * Flash & Environment
 143  */
 144 #ifdef CONFIG_NAND
 145 #define CONFIG_ENV_OFFSET               0x0 /* Block 0--not used by bootcode */
 146 #define CONFIG_ENV_SIZE                 (128 << 9)
 147 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 148 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 149 #define CONFIG_SYS_NAND_PAGE_2K
 150 #define CONFIG_SYS_NAND_CS              3
 151 #define CONFIG_SYS_NAND_BASE            DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
 152 #define CONFIG_SYS_NAND_MASK_CLE        0x10
 153 #define CONFIG_SYS_NAND_MASK_ALE        0x8
 154 #undef CONFIG_SYS_NAND_HW_ECC
 155 #define CONFIG_SYS_MAX_NAND_DEVICE      1 /* Max number of NAND devices */
 156 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 157 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
 158 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 159 #define CONFIG_SYS_NAND_PAGE_SIZE       (2 << 10)
 160 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)
 161 #define CONFIG_SYS_NAND_U_BOOT_SIZE     SZ_512K
 162 #define CONFIG_SYS_NAND_U_BOOT_DST      0xc1080000
 163 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 164 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
 165                                         CONFIG_SYS_NAND_U_BOOT_SIZE - \
 166                                         CONFIG_SYS_MALLOC_LEN -       \
 167                                         GENERATED_GBL_DATA_SIZE)
 168 #define CONFIG_SYS_NAND_ECCPOS          {                               \
 169                                 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,     \
 170                                 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
 171                                 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
 172                                 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
 173 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 174 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 175 #define CONFIG_SYS_NAND_ECCSIZE         512
 176 #define CONFIG_SYS_NAND_ECCBYTES        10
 177 #define CONFIG_SYS_NAND_OOBSIZE         64
 178 #define CONFIG_SPL_NAND_BASE
 179 #define CONFIG_SPL_NAND_DRIVERS
 180 #define CONFIG_SPL_NAND_ECC
 181 #define CONFIG_SPL_NAND_LOAD
 182 #endif
 183
 184 #ifdef CONFIG_SYS_USE_NOR
 185 #define CONFIG_FLASH_CFI_DRIVER
 186 #define CONFIG_SYS_FLASH_CFI
 187 #define CONFIG_SYS_FLASH_PROTECTION
 188 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* max number of flash banks */
 189 #define CONFIG_SYS_FLASH_SECT_SZ        (128 << 10) /* 128KB */
 190 #define CONFIG_ENV_OFFSET               (CONFIG_SYS_FLASH_SECT_SZ * 3)
 191 #define CONFIG_ENV_SIZE                 (128 << 10)
 192 #define CONFIG_SYS_FLASH_BASE           DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
 193 #define PHYS_FLASH_SIZE                 (8 << 20) /* Flash size 8MB */
 194 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
 195                + 3)
 196 #define CONFIG_ENV_SECT_SIZE            CONFIG_SYS_FLASH_SECT_SZ
 197 #endif
 198
 199 #ifdef CONFIG_USE_SPIFLASH
 200 #define CONFIG_ENV_SIZE                 (64 << 10)
 201 #define CONFIG_ENV_OFFSET               (256 << 10)
 202 #define CONFIG_ENV_SECT_SIZE            (64 << 10)
 203 #endif
 204
 205 /*
 206  * Network & Ethernet Configuration
 207  */
 208 #ifdef CONFIG_DRIVER_TI_EMAC
 209 #define CONFIG_MII
 210 #undef  CONFIG_DRIVER_TI_EMAC_USE_RMII
 211 #define CONFIG_BOOTP_DEFAULT
 212 #define CONFIG_BOOTP_DNS2
 213 #define CONFIG_BOOTP_SEND_HOSTNAME
 214 #define CONFIG_NET_RETRY_COUNT  10
 215 #endif
 216
 217 /*
 218  * U-Boot general configuration
 219  */
 220 #define CONFIG_MISC_INIT_R
 221 #define CONFIG_BOOTFILE         "zImage" /* Boot file name */
 222 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 223 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 224 #define CONFIG_SYS_LOAD_ADDR    (PHYS_SDRAM_1 + 0x700000)
 225 #define CONFIG_MX_CYCLIC
 226
 227 /*
 228  * Linux Information
 229  */
 230 #define LINUX_BOOT_PARAM_ADDR   (PHYS_SDRAM_1 + 0x100)
 231 #define CONFIG_CMDLINE_TAG
 232 #define CONFIG_REVISION_TAG
 233 #define CONFIG_SETUP_MEMORY_TAGS
 234 #define CONFIG_BOOTCOMMAND \
 235                 "run envboot; " \
 236                 "run mmcboot; "
 237
 238 #define DEFAULT_LINUX_BOOT_ENV \
 239         "loadaddr=0xc0700000\0" \
 240         "fdtaddr=0xc0600000\0" \
 241         "scriptaddr=0xc0600000\0"
 242
 243 #include <environment/ti/mmc.h>
 244
 245 #define CONFIG_EXTRA_ENV_SETTINGS \
 246         DEFAULT_LINUX_BOOT_ENV \
 247         DEFAULT_MMC_TI_ARGS \
 248         "bootpart=0:2\0" \
 249         "bootdir=/boot\0" \
 250         "bootfile=zImage\0" \
 251         "fdtfile=da850-lcdk.dtb\0" \
 252         "boot_fdt=yes\0" \
 253         "boot_fit=0\0" \
 254         "console=ttyS2,115200n8\0"
 255
 256 #ifdef CONFIG_CMD_BDI
 257 #define CONFIG_CLOCKS
 258 #endif
 259
 260 #if !defined(CONFIG_NAND) && \
 261         !defined(CONFIG_SYS_USE_NOR) && \
 262         !defined(CONFIG_USE_SPIFLASH)
 263 #define CONFIG_ENV_SIZE         (16 << 10)
 264 #endif
 265
 266 /* SD/MMC */
 267
 268 #ifdef CONFIG_ENV_IS_IN_MMC
 269 #undef CONFIG_ENV_SIZE
 270 #undef CONFIG_ENV_OFFSET
 271 #define CONFIG_ENV_SIZE         (16 << 10)      /* 16 KiB */
 272 #define CONFIG_ENV_OFFSET       (51 << 9)       /* Sector 51 */
 273 #endif
 274
 275 #ifndef CONFIG_DIRECT_NOR_BOOT
 276 /* defines for SPL */
 277 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE - \
 278                                                 CONFIG_SYS_MALLOC_LEN)
 279 #define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
 280 #define CONFIG_SPL_STACK        0x8001ff00
 281 #define CONFIG_SPL_TEXT_BASE    0x80000000
 282 #define CONFIG_SPL_MAX_FOOTPRINT        32768
 283 #define CONFIG_SPL_PAD_TO       32768
 284 #endif
 285
 286 /* additions for new relocation code, must added to all boards */
 287 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
 288 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
 289                                         GENERATED_GBL_DATA_SIZE)
 290
 291 #include <asm/arch/hardware.h>
 292
 293 #endif /* __CONFIG_H */