1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Based on davinci_dvevm.h. Original Copyrights follow:
7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
20 #define CONFIG_SYS_OSCIN_FREQ 24000000
21 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
22 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
27 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
28 #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
29 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
31 #define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
32 #define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
34 /* memtest start addr */
36 /* memtest will be run on 16MB */
38 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
39 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
40 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
41 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
42 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
43 DAVINCI_SYSCFG_SUSPSRC_I2C)
49 /* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
50 #define CONFIG_SYS_DA850_PLL0_PLLM 18
51 #define CONFIG_SYS_DA850_PLL1_PLLM 21
54 * DDR2 memory configuration
56 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
57 DV_DDR_PHY_EXT_STRBEN | \
58 (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
60 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \
61 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
62 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
63 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
64 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
65 (4 << DV_DDR_SDCR_CL_SHIFT) | \
66 (3 << DV_DDR_SDCR_IBANK_SHIFT) | \
67 (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
69 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
70 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
72 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
73 (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \
74 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
75 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
76 (2 << DV_DDR_SDTMR1_WR_SHIFT) | \
77 (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \
78 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
79 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
80 (1 << DV_DDR_SDTMR1_WTR_SHIFT))
82 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
83 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
84 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
85 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
86 (20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
87 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
88 (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
89 (2 << DV_DDR_SDTMR2_CKE_SHIFT))
91 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492
92 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
97 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
99 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
100 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
105 #define CONFIG_SYS_DAVINCI_I2C_SPEED 25000
106 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
107 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
110 * Flash & Environment
112 #ifdef CONFIG_MTD_RAW_NAND
113 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
114 #define CONFIG_SYS_NAND_PAGE_2K
115 #define CONFIG_SYS_NAND_CS 3
116 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
117 #define CONFIG_SYS_NAND_MASK_CLE 0x10
118 #define CONFIG_SYS_NAND_MASK_ALE 0x8
119 #undef CONFIG_SYS_NAND_HW_ECC
120 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
121 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
122 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
123 #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
124 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
125 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
126 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
127 CONFIG_SYS_NAND_U_BOOT_SIZE - \
128 CONFIG_SYS_MALLOC_LEN - \
129 GENERATED_GBL_DATA_SIZE)
130 #define CONFIG_SYS_NAND_ECCPOS { \
131 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
132 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
133 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
134 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
135 #define CONFIG_SYS_NAND_ECCSIZE 512
136 #define CONFIG_SYS_NAND_ECCBYTES 10
140 * Network & Ethernet Configuration
142 #ifdef CONFIG_DRIVER_TI_EMAC
143 #define CONFIG_NET_RETRY_COUNT 10
147 * U-Boot general configuration
149 #define CONFIG_BOOTFILE "zImage" /* Boot file name */
150 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
151 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
156 #define CONFIG_USB_OHCI_NEW
157 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
162 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
164 #define DEFAULT_LINUX_BOOT_ENV \
165 "loadaddr=0xc0700000\0" \
166 "fdtaddr=0xc0600000\0" \
167 "scriptaddr=0xc0600000\0"
169 #include <environment/ti/mmc.h>
171 #define CONFIG_EXTRA_ENV_SETTINGS \
172 DEFAULT_LINUX_BOOT_ENV \
173 DEFAULT_MMC_TI_ARGS \
176 "bootfile=zImage\0" \
177 "fdtfile=da850-lcdk.dtb\0" \
180 "console=ttyS2,115200n8\0"
182 #ifdef CONFIG_CMD_BDI
183 #define CONFIG_CLOCKS
188 /* defines for SPL */
189 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
190 CONFIG_SYS_MALLOC_LEN)
191 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
192 #define CONFIG_SPL_STACK 0x8001ff00
193 #define CONFIG_SPL_MAX_FOOTPRINT 32768
194 #define CONFIG_SPL_PAD_TO 32768
196 /* additions for new relocation code, must added to all boards */
197 #define CONFIG_SYS_SDRAM_BASE 0xc0000000
198 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
199 GENERATED_GBL_DATA_SIZE)
201 #include <asm/arch/hardware.h>
203 #endif /* __CONFIG_H */