4227610566dcd76acf05b3b1bb1e49ec36679398
[platform/kernel/u-boot.git] / include / configs / omapl138_lcdk.h
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4  *
5  * Based on davinci_dvevm.h. Original Copyrights follow:
6  *
7  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
8  */
9
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12
13 /*
14  * Board
15  */
16
17 /*
18  * SoC Configuration
19  */
20 #define CONFIG_SYS_CLK_FREQ             clk_get(DAVINCI_ARM_CLKID)
21 #define CONFIG_SYS_OSCIN_FREQ           24000000
22 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
23 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
24 #define CONFIG_SYS_HZ                   1000
25
26 /*
27  * Memory Info
28  */
29 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
30 #define PHYS_SDRAM_1_SIZE       (128 << 20) /* SDRAM size 128MB */
31 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
32
33 #define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
34 #define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
35
36 /* memtest start addr */
37
38 /* memtest will be run on 16MB */
39
40 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
41         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
42         DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
43         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
44         DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
45         DAVINCI_SYSCFG_SUSPSRC_I2C)
46
47 /*
48  * PLL configuration
49  */
50
51 /* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
52 #define CONFIG_SYS_DA850_PLL0_PLLM     18
53 #define CONFIG_SYS_DA850_PLL1_PLLM     21
54
55 /*
56  * DDR2 memory configuration
57  */
58 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
59                                         DV_DDR_PHY_EXT_STRBEN | \
60                                         (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
61
62 #define CONFIG_SYS_DA850_DDR2_SDBCR (             \
63         (1 << DV_DDR_SDCR_DDR2EN_SHIFT)         | \
64         (1 << DV_DDR_SDCR_DDREN_SHIFT)          | \
65         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT)        | \
66         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)      | \
67         (4 << DV_DDR_SDCR_CL_SHIFT)             | \
68         (3 << DV_DDR_SDCR_IBANK_SHIFT)          | \
69         (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
70
71 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
72 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
73
74 #define CONFIG_SYS_DA850_DDR2_SDTIMR (            \
75         (19 << DV_DDR_SDTMR1_RFC_SHIFT)         | \
76         (1 << DV_DDR_SDTMR1_RP_SHIFT)           | \
77         (1 << DV_DDR_SDTMR1_RCD_SHIFT)          | \
78         (2 << DV_DDR_SDTMR1_WR_SHIFT)           | \
79         (6 << DV_DDR_SDTMR1_RAS_SHIFT)          | \
80         (8 << DV_DDR_SDTMR1_RC_SHIFT)           | \
81         (1 << DV_DDR_SDTMR1_RRD_SHIFT)          | \
82         (1 << DV_DDR_SDTMR1_WTR_SHIFT))
83
84 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (           \
85         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT)       | \
86         (2 << DV_DDR_SDTMR2_XP_SHIFT)           | \
87         (0 << DV_DDR_SDTMR2_ODT_SHIFT)          | \
88         (20 << DV_DDR_SDTMR2_XSNR_SHIFT)        | \
89         (199 << DV_DDR_SDTMR2_XSRD_SHIFT)       | \
90         (1 << DV_DDR_SDTMR2_RTP_SHIFT)          | \
91         (2 << DV_DDR_SDTMR2_CKE_SHIFT))
92
93 #define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000492
94 #define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
95
96 /*
97  * Serial Driver info
98  */
99 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
100
101 #define CONFIG_SYS_SPI_BASE             DAVINCI_SPI1_BASE
102 #define CONFIG_SYS_SPI_CLK              clk_get(DAVINCI_SPI1_CLKID)
103
104 /*
105  * I2C Configuration
106  */
107 #define CONFIG_SYS_DAVINCI_I2C_SPEED    25000
108 #define CONFIG_SYS_DAVINCI_I2C_SLAVE    10 /* Bogus, master-only in U-Boot */
109 #define CONFIG_SYS_I2C_EXPANDER_ADDR    0x20
110
111 /*
112  * Flash & Environment
113  */
114 #ifdef CONFIG_MTD_RAW_NAND
115 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
116 #define CONFIG_SYS_NAND_PAGE_2K
117 #define CONFIG_SYS_NAND_CS              3
118 #define CONFIG_SYS_NAND_BASE            DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
119 #define CONFIG_SYS_NAND_MASK_CLE        0x10
120 #define CONFIG_SYS_NAND_MASK_ALE        0x8
121 #undef CONFIG_SYS_NAND_HW_ECC
122 #define CONFIG_SYS_MAX_NAND_DEVICE      1 /* Max number of NAND devices */
123 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
124 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
125 #define CONFIG_SYS_NAND_U_BOOT_SIZE     SZ_512K
126 #define CONFIG_SYS_NAND_U_BOOT_DST      0xc1080000
127 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
128 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
129                                         CONFIG_SYS_NAND_U_BOOT_SIZE - \
130                                         CONFIG_SYS_MALLOC_LEN -       \
131                                         GENERATED_GBL_DATA_SIZE)
132 #define CONFIG_SYS_NAND_ECCPOS          {                               \
133                                 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,     \
134                                 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
135                                 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
136                                 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
137 #define CONFIG_SYS_NAND_ECCSIZE         512
138 #define CONFIG_SYS_NAND_ECCBYTES        10
139 #endif
140
141 /*
142  * Network & Ethernet Configuration
143  */
144 #ifdef CONFIG_DRIVER_TI_EMAC
145 #define CONFIG_NET_RETRY_COUNT  10
146 #endif
147
148 /*
149  * U-Boot general configuration
150  */
151 #define CONFIG_BOOTFILE         "zImage" /* Boot file name */
152 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
153 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
154
155 /*
156  * USB Configs
157  */
158 #define CONFIG_USB_OHCI_NEW
159 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
160
161 /*
162  * Linux Information
163  */
164 #define LINUX_BOOT_PARAM_ADDR   (PHYS_SDRAM_1 + 0x100)
165 #define CONFIG_BOOTCOMMAND \
166                 "run envboot; " \
167                 "run mmcboot; "
168
169 #define DEFAULT_LINUX_BOOT_ENV \
170         "loadaddr=0xc0700000\0" \
171         "fdtaddr=0xc0600000\0" \
172         "scriptaddr=0xc0600000\0"
173
174 #include <environment/ti/mmc.h>
175
176 #define CONFIG_EXTRA_ENV_SETTINGS \
177         DEFAULT_LINUX_BOOT_ENV \
178         DEFAULT_MMC_TI_ARGS \
179         "bootpart=0:2\0" \
180         "bootdir=/boot\0" \
181         "bootfile=zImage\0" \
182         "fdtfile=da850-lcdk.dtb\0" \
183         "boot_fdt=yes\0" \
184         "boot_fit=0\0" \
185         "console=ttyS2,115200n8\0"
186
187 #ifdef CONFIG_CMD_BDI
188 #define CONFIG_CLOCKS
189 #endif
190
191 /* SD/MMC */
192
193 /* defines for SPL */
194 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE - \
195                                                 CONFIG_SYS_MALLOC_LEN)
196 #define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
197 #define CONFIG_SPL_STACK        0x8001ff00
198 #define CONFIG_SPL_MAX_FOOTPRINT        32768
199 #define CONFIG_SPL_PAD_TO       32768
200
201 /* additions for new relocation code, must added to all boards */
202 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
203 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
204                                         GENERATED_GBL_DATA_SIZE)
205
206 #include <asm/arch/hardware.h>
207
208 #endif /* __CONFIG_H */