3 * Texas Instruments Incorporated.
4 * Aneesh V <aneesh@ti.com>
5 * Steve Sakoman <steve@sakoman.com>
7 * Configuration settings for the TI SDP4430 board.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * High Level Configuration Options
34 #define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
35 #define CONFIG_OMAP 1 /* in a TI OMAP core */
36 #define CONFIG_OMAP44XX 1 /* which is a 44XX */
37 #define CONFIG_OMAP4430 1 /* which is in a 4430 */
38 #define CONFIG_4430SDP 1 /* working with SDP */
39 #define CONFIG_ARCH_CPU_INIT
42 #include <asm/arch/cpu.h>
43 #include <asm/arch/omap4.h>
45 /* Display CPU and Board Info */
46 #define CONFIG_DISPLAY_CPUINFO 1
47 #define CONFIG_DISPLAY_BOARDINFO 1
50 #define V_OSCK 38400000 /* Clock output from T2 */
53 #undef CONFIG_USE_IRQ /* no support for IRQs */
54 #define CONFIG_MISC_INIT_R
56 #define CONFIG_OF_LIBFDT 1
58 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
59 #define CONFIG_SETUP_MEMORY_TAGS 1
60 #define CONFIG_INITRD_TAG 1
61 #define CONFIG_REVISION_TAG 1
64 * Size of malloc() pool
65 * Total Size Environment - 128k
68 #define CONFIG_ENV_SIZE (128 << 10)
69 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
71 #define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE
78 * serial port - NS16550 compatible
80 #define V_NS16550_CLK 48000000
82 #define CONFIG_SYS_NS16550
83 #define CONFIG_SYS_NS16550_SERIAL
84 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
85 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
86 #define CONFIG_CONS_INDEX 3
87 #define CONFIG_SYS_NS16550_COM3 UART3_BASE
89 #define CONFIG_BAUDRATE 115200
90 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
93 #define CONFIG_HARD_I2C 1
94 #define CONFIG_SYS_I2C_SPEED 100000
95 #define CONFIG_SYS_I2C_SLAVE 1
96 #define CONFIG_SYS_I2C_BUS 0
97 #define CONFIG_SYS_I2C_BUS_SELECT 1
98 #define CONFIG_DRIVER_OMAP34XX_I2C 1
99 #define CONFIG_I2C_MULTI_BUS 1
102 #define CONFIG_TWL6030_POWER 1
103 #define CONFIG_CMD_BAT 1
106 #define CONFIG_GENERIC_MMC 1
108 #define CONFIG_OMAP_HSMMC 1
109 #define CONFIG_SYS_MMC_SET_DEV 1
110 #define CONFIG_DOS_PARTITION 1
112 /* MMC ENV related defines */
113 #define CONFIG_ENV_IS_IN_MMC 1
114 #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
115 #define CONFIG_ENV_OFFSET 0xE0000
118 #define CONFIG_MUSB_UDC 1
119 #define CONFIG_USB_OMAP3 1
121 /* USB device configuration */
122 #define CONFIG_USB_DEVICE 1
123 #define CONFIG_USB_TTY 1
124 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
127 #define CONFIG_SYS_NO_FLASH 1
129 /* commands to include */
130 #include <config_cmd_default.h>
132 /* Enabled commands */
133 #define CONFIG_CMD_EXT2 /* EXT2 Support */
134 #define CONFIG_CMD_FAT /* FAT support */
135 #define CONFIG_CMD_I2C /* I2C serial bus support */
136 #define CONFIG_CMD_MMC /* MMC support */
137 #define CONFIG_CMD_SAVEENV
139 /* Disabled commands */
140 #undef CONFIG_CMD_NET
141 #undef CONFIG_CMD_NFS
142 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
143 #undef CONFIG_CMD_IMLS /* List all found images */
149 #define CONFIG_BOOTDELAY 3
151 #define CONFIG_ENV_OVERWRITE
153 #define CONFIG_EXTRA_ENV_SETTINGS \
154 "loadaddr=0x82000000\0" \
155 "console=ttyS2,115200n8\0" \
159 "mmcroot=/dev/mmcblk0p2 rw\0" \
160 "mmcrootfstype=ext3 rootwait\0" \
161 "mmcargs=setenv bootargs console=${console} " \
164 "rootfstype=${mmcrootfstype}\0" \
165 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
166 "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
167 "source ${loadaddr}\0" \
168 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
169 "mmcboot=echo Booting from mmc${mmcdev} ...; " \
171 "bootm ${loadaddr}\0" \
173 #define CONFIG_BOOTCOMMAND \
174 "if mmc rescan ${mmcdev}; then " \
175 "if run loadbootscript; then " \
178 "if run loaduimage; then " \
184 #define CONFIG_AUTO_COMPLETE 1
187 * Miscellaneous configurable options
190 #define CONFIG_SYS_LONGHELP /* undef to save memory */
191 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
192 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
193 #define CONFIG_SYS_PROMPT "OMAP4430 SDP # "
194 #define CONFIG_SYS_CBSIZE 256
195 /* Print Buffer Size */
196 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
197 sizeof(CONFIG_SYS_PROMPT) + 16)
198 #define CONFIG_SYS_MAXARGS 16
199 /* Boot Argument Buffer Size */
200 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
205 #define CONFIG_SYS_MEMTEST_START 0x80000000
206 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20))
208 /* Default load address */
209 #define CONFIG_SYS_LOAD_ADDR 0x80000000
211 /* Use General purpose timer 1 */
212 #define CONFIG_SYS_TIMERBASE GPT2_BASE
213 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
214 #define CONFIG_SYS_HZ 1000
219 * The stack sizes are set up in start.S using the settings below
221 #define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
222 #ifdef CONFIG_USE_IRQ
223 #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
224 #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
229 * Even though we use two CS all the memory
230 * is mapped to one contiguous block
232 #define CONFIG_NR_DRAM_BANKS 1
234 #define CONFIG_SYS_SDRAM_BASE 0x80000000
235 #define CONFIG_SYS_INIT_RAM_ADDR 0x4030D800
236 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
237 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
238 CONFIG_SYS_INIT_RAM_SIZE - \
239 GENERATED_GBL_DATA_SIZE)
241 #ifndef CONFIG_SYS_L2CACHE_OFF
242 #define CONFIG_SYS_L2_PL310 1
243 #define CONFIG_SYS_PL310_BASE 0x48242000
246 /* Defines for SDRAM init */
247 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
248 #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
251 #endif /* __CONFIG_H */