include/configs/omap3_zoom1.h

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Texas Instruments.
   4  * Richard Woodruff <r-woodruff2@ti.com>
   5  * Syed Mohammed Khasim <x0khasim@ti.com>
   6  * Nishanth Menon <nm@ti.com>
   7  *
   8  * Configuration settings for the TI OMAP3430 Zoom MDK board.
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 /*
  33  * High Level Configuration Options
  34  */
  35 #define CONFIG_OMAP             1       /* in a TI OMAP core */
  36 #define CONFIG_OMAP34XX         1       /* which is a 34XX */
  37 #define CONFIG_OMAP3_ZOOM1      1       /* working with Zoom MDK Rev1 */
  38
  39 #define CONFIG_SDRC     /* The chip has SDRC controller */
  40
  41 #include <asm/arch/cpu.h>               /* get chip and board defs */
  42 #include <asm/arch/omap3.h>
  43
  44 /*
  45  * Display CPU and Board information
  46  */
  47 #define CONFIG_DISPLAY_CPUINFO          1
  48 #define CONFIG_DISPLAY_BOARDINFO        1
  49
  50 /* Clock Defines */
  51 #define V_OSCK                  26000000        /* Clock output from T2 */
  52 #define V_SCLK                  (V_OSCK >> 1)
  53
  54 #define CONFIG_MISC_INIT_R
  55
  56 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
  57 #define CONFIG_SETUP_MEMORY_TAGS        1
  58 #define CONFIG_INITRD_TAG               1
  59 #define CONFIG_REVISION_TAG             1
  60
  61 #define CONFIG_OF_LIBFDT                1
  62
  63 /*
  64  * Size of malloc() pool
  65  */
  66 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB */
  67                                                 /* Sector */
  68 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (128 << 10))
  69
  70 /*
  71  * Hardware drivers
  72  */
  73
  74 /*
  75  * NS16550 Configuration
  76  */
  77 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  78
  79 #define CONFIG_SYS_NS16550
  80 #define CONFIG_SYS_NS16550_SERIAL
  81 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  82 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  83
  84 /*
  85  * select serial console configuration
  86  */
  87 #define CONFIG_CONS_INDEX               3
  88 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  89 #define CONFIG_SERIAL3                  3       /* UART3 */
  90
  91 /* allow to overwrite serial and ethaddr */
  92 #define CONFIG_ENV_OVERWRITE
  93 #define CONFIG_BAUDRATE                 115200
  94 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  95                                         115200}
  96 #define CONFIG_GENERIC_MMC              1
  97 #define CONFIG_MMC                      1
  98 #define CONFIG_OMAP_HSMMC               1
  99 #define CONFIG_DOS_PARTITION            1
 100
 101 /* USB */
 102 #define CONFIG_MUSB_UDC                 1
 103 #define CONFIG_USB_OMAP3                1
 104 #define CONFIG_TWL4030_USB              1
 105
 106 /* USB device configuration */
 107 #define CONFIG_USB_DEVICE               1
 108 #define CONFIG_USB_TTY                  1
 109 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    1
 110 /* Change these to suit your needs */
 111 #define CONFIG_USBD_VENDORID            0x0451
 112 #define CONFIG_USBD_PRODUCTID           0x5678
 113 #define CONFIG_USBD_MANUFACTURER        "Texas Instruments"
 114 #define CONFIG_USBD_PRODUCT_NAME        "Zoom1"
 115
 116 /* commands to include */
 117 #include <config_cmd_default.h>
 118
 119 #define CONFIG_CMD_EXT2         /* EXT2 Support                 */
 120 #define CONFIG_CMD_FAT          /* FAT support                  */
 121 #define CONFIG_CMD_JFFS2        /* JFFS2 Support                */
 122
 123 #define CONFIG_CMD_I2C          /* I2C serial bus support       */
 124 #define CONFIG_CMD_MMC          /* MMC support                  */
 125 #define CONFIG_CMD_NAND         /* NAND support                 */
 126 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
 127
 128 #undef CONFIG_CMD_FLASH         /* flinfo, erase, protect       */
 129 #undef CONFIG_CMD_FPGA          /* FPGA configuration Support   */
 130 #undef CONFIG_CMD_IMI           /* iminfo                       */
 131 #undef CONFIG_CMD_IMLS          /* List all found images        */
 132 #undef CONFIG_CMD_NET           /* bootp, tftpboot, rarpboot    */
 133 #undef CONFIG_CMD_NFS           /* NFS support                  */
 134
 135 #define CONFIG_SYS_NO_FLASH
 136 #define CONFIG_HARD_I2C                 1
 137 #define CONFIG_SYS_I2C_SPEED            100000
 138 #define CONFIG_SYS_I2C_SLAVE            1
 139 #define CONFIG_SYS_I2C_BUS              0
 140 #define CONFIG_SYS_I2C_BUS_SELECT       1
 141 #define CONFIG_DRIVER_OMAP34XX_I2C      1
 142
 143 /*
 144  * TWL4030
 145  */
 146 #define CONFIG_TWL4030_POWER            1
 147 #define CONFIG_TWL4030_LED              1
 148
 149 /*
 150  * Board NAND Info.
 151  */
 152 #define CONFIG_NAND_OMAP_GPMC
 153 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 154                                                         /* to access nand */
 155 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 156                                                         /* to access nand at */
 157                                                         /* CS0 */
 158 #define GPMC_NAND_ECC_LP_x16_LAYOUT     1
 159
 160 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
 161                                                         /* devices */
 162 #define CONFIG_JFFS2_NAND
 163 /* nand device jffs2 lives on */
 164 #define CONFIG_JFFS2_DEV                "nand0"
 165 /* start of jffs2 partition */
 166 #define CONFIG_JFFS2_PART_OFFSET        0x680000
 167 #define CONFIG_JFFS2_PART_SIZE          0xf980000       /* size of jffs2 */
 168                                                         /* partition */
 169
 170 /* Environment information */
 171 #define CONFIG_BOOTDELAY                10
 172
 173 #define CONFIG_EXTRA_ENV_SETTINGS \
 174         "loadaddr=0x82000000\0" \
 175         "usbtty=cdc_acm\0" \
 176         "console=ttyS2,115200n8\0" \
 177         "mmcdev=0\0" \
 178         "videomode=1024x768@60,vxres=1024,vyres=768\0" \
 179         "videospec=omapfb:vram:2M,vram:4M\0" \
 180         "mmcargs=setenv bootargs console=${console} " \
 181                 "video=${videospec},mode:${videomode} " \
 182                 "root=/dev/mmcblk0p2 rw " \
 183                 "rootfstype=ext3 rootwait\0" \
 184         "nandargs=setenv bootargs console=${console} " \
 185                 "video=${videospec},mode:${videomode} " \
 186                 "root=/dev/mtdblock4 rw " \
 187                 "rootfstype=jffs2\0" \
 188         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 189         "bootscript=echo Running bootscript from mmc ...; " \
 190                 "source ${loadaddr}\0" \
 191         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 192         "mmcboot=echo Booting from mmc ...; " \
 193                 "run mmcargs; " \
 194                 "bootm ${loadaddr}\0" \
 195         "nandboot=echo Booting from nand ...; " \
 196                 "run nandargs; " \
 197                 "nand read ${loadaddr} 280000 400000; " \
 198                 "bootm ${loadaddr}\0" \
 199
 200 #define CONFIG_BOOTCOMMAND \
 201         "mmc dev ${mmcdev}; if mmc rescan; then " \
 202                 "if run loadbootscript; then " \
 203                         "run bootscript; " \
 204                 "else " \
 205                         "if run loaduimage; then " \
 206                                 "run mmcboot; " \
 207                         "else run nandboot; " \
 208                         "fi; " \
 209                 "fi; " \
 210         "else run nandboot; fi"
 211
 212 #define CONFIG_AUTO_COMPLETE            1
 213 /*
 214  * Miscellaneous configurable options
 215  */
 216 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 217 #define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
 218 #define CONFIG_SYS_PROMPT               "OMAP3 Zoom1 # "
 219 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 220 /* Print Buffer Size */
 221 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 222                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 223 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 224 /* Boot Argument Buffer Size */
 225 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 226
 227 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)     /* memtest */
 228                                                                 /* works on */
 229 #define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 230                                         0x01F00000) /* 31MB */
 231
 232 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0)     /* default */
 233                                                         /* load address */
 234
 235 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 236 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 237 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 238 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
 239                                          CONFIG_SYS_INIT_RAM_SIZE - \
 240                                          GENERATED_GBL_DATA_SIZE)
 241 /*
 242  * OMAP3 has 12 GP timers, they can be driven by the system clock
 243  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 244  * This rate is divided by a local divisor.
 245  */
 246 #define CONFIG_SYS_TIMERBASE            OMAP34XX_GPT2
 247 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 248 #define CONFIG_SYS_HZ                   1000
 249
 250 /*-----------------------------------------------------------------------
 251  * Physical Memory Map
 252  */
 253 #define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
 254 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 255 #define PHYS_SDRAM_2            OMAP34XX_SDRC_CS1
 256
 257 /*-----------------------------------------------------------------------
 258  * FLASH and environment organization
 259  */
 260
 261 /* **** PISMO SUPPORT *** */
 262
 263 /* Configure the PISMO */
 264 #define PISMO1_NAND_SIZE                GPMC_SIZE_128M
 265 #define PISMO1_ONEN_SIZE                GPMC_SIZE_128M
 266
 267 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 268
 269 #if defined(CONFIG_CMD_NAND)
 270 #define CONFIG_SYS_FLASH_BASE           PISMO1_NAND_BASE
 271 #endif
 272
 273 /* Monitor at start of flash */
 274 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 275 #define CONFIG_SYS_ONENAND_BASE         ONENAND_MAP
 276
 277 #define CONFIG_ENV_IS_IN_NAND           1
 278 #define ONENAND_ENV_OFFSET              0x260000 /* environment starts here */
 279 #define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 280
 281 #define CONFIG_SYS_ENV_SECT_SIZE        (128 << 10)     /* 128 KiB */
 282 #define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 283 #define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
 284
 285 #define CONFIG_SYS_CACHELINE_SIZE       64
 286
 287 #endif                          /* __CONFIG_H */