3 * Grazvydas Ignotas <notasas@gmail.com>
5 * Configuration settings for the OMAP3 Pandora.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * High Level Configuration Options
29 #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
30 #define CONFIG_OMAP 1 /* in a TI OMAP core */
31 #define CONFIG_OMAP34XX 1 /* which is a 34XX */
32 #define CONFIG_OMAP3430 1 /* which is in a 3430 */
33 #define CONFIG_OMAP3_PANDORA 1 /* working with pandora */
35 #include <asm/arch/cpu.h> /* get chip and board defs */
36 #include <asm/arch/omap3.h>
39 * Display CPU and Board information
41 #define CONFIG_DISPLAY_CPUINFO 1
42 #define CONFIG_DISPLAY_BOARDINFO 1
45 #define V_OSCK 26000000 /* Clock output from T2 */
46 #define V_SCLK (V_OSCK >> 1)
48 #undef CONFIG_USE_IRQ /* no support for IRQs */
49 #define CONFIG_MISC_INIT_R
51 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
52 #define CONFIG_SETUP_MEMORY_TAGS 1
53 #define CONFIG_INITRD_TAG 1
54 #define CONFIG_REVISION_TAG 1
57 * Size of malloc() pool
59 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
61 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
62 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
70 * NS16550 Configuration
72 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
74 #define CONFIG_SYS_NS16550
75 #define CONFIG_SYS_NS16550_SERIAL
76 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
77 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
80 * select serial console configuration
82 #define CONFIG_CONS_INDEX 3
83 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
84 #define CONFIG_SERIAL3 3
86 /* allow to overwrite serial and ethaddr */
87 #define CONFIG_ENV_OVERWRITE
88 #define CONFIG_BAUDRATE 115200
89 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
92 #define CONFIG_OMAP3_MMC 1
93 #define CONFIG_DOS_PARTITION 1
95 /* commands to include */
96 #include <config_cmd_default.h>
98 #define CONFIG_CMD_EXT2 /* EXT2 Support */
99 #define CONFIG_CMD_FAT /* FAT support */
100 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
102 #define CONFIG_CMD_I2C /* I2C serial bus support */
103 #define CONFIG_CMD_MMC /* MMC support */
104 #define CONFIG_CMD_NAND /* NAND support */
106 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
107 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
108 #undef CONFIG_CMD_IMI /* iminfo */
109 #undef CONFIG_CMD_IMLS /* List all found images */
110 #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
111 #undef CONFIG_CMD_NFS /* NFS support */
113 #define CONFIG_SYS_NO_FLASH
114 #define CONFIG_HARD_I2C 1
115 #define CONFIG_SYS_I2C_SPEED 100000
116 #define CONFIG_SYS_I2C_SLAVE 1
117 #define CONFIG_SYS_I2C_BUS 0
118 #define CONFIG_SYS_I2C_BUS_SELECT 1
119 #define CONFIG_DRIVER_OMAP34XX_I2C 1
124 #define CONFIG_TWL4030_POWER 1
125 #define CONFIG_TWL4030_LED 1
130 #define CONFIG_NAND_OMAP_GPMC
131 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
133 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
136 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1
138 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
141 #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
143 #define CONFIG_JFFS2_NAND
144 /* nand device jffs2 lives on */
145 #define CONFIG_JFFS2_DEV "nand0"
146 /* start of jffs2 partition */
147 #define CONFIG_JFFS2_PART_OFFSET 0x680000
148 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
151 /* Environment information */
152 #define CONFIG_BOOTDELAY 1
154 #define CONFIG_EXTRA_ENV_SETTINGS \
155 "loadaddr=0x82000000\0" \
156 "console=ttyS0,115200n8\0" \
157 "videospec=omapfb:vram:2M,vram:4M\0" \
158 "mmcargs=setenv bootargs console=${console} " \
159 "video=${videospec} " \
160 "root=/dev/mmcblk0p2 rw " \
161 "rootfstype=ext3 rootwait\0" \
162 "nandargs=setenv bootargs console=${console} " \
163 "video=${videospec} " \
164 "root=/dev/mtdblock4 rw " \
165 "rootfstype=jffs2\0" \
166 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
167 "bootscript=echo Running bootscript from mmc ...; " \
168 "source ${loadaddr}\0" \
169 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
170 "mmcboot=echo Booting from mmc ...; " \
172 "bootm ${loadaddr}\0" \
173 "nandboot=echo Booting from nand ...; " \
175 "nand read ${loadaddr} 280000 400000; " \
176 "bootm ${loadaddr}\0" \
178 #define CONFIG_BOOTCOMMAND \
179 "if mmc init; then " \
180 "if run loadbootscript; then " \
183 "if run loaduimage; then " \
185 "else run nandboot; " \
188 "else run nandboot; fi"
190 #define CONFIG_AUTO_COMPLETE 1
192 * Miscellaneous configurable options
194 #define V_PROMPT "Pandora # "
196 #define CONFIG_SYS_LONGHELP /* undef to save memory */
197 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
198 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
199 #define CONFIG_SYS_PROMPT V_PROMPT
200 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
201 /* Print Buffer Size */
202 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
203 sizeof(CONFIG_SYS_PROMPT) + 16)
204 #define CONFIG_SYS_MAXARGS 16 /* max number of command */
206 /* Boot Argument Buffer Size */
207 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
208 /* memtest works on */
209 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
210 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
211 0x01F00000) /* 31MB */
213 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
217 * OMAP3 has 12 GP timers, they can be driven by the system clock
218 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
219 * This rate is divided by a local divisor.
221 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
222 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
223 #define CONFIG_SYS_HZ 1000
225 /*-----------------------------------------------------------------------
228 * The stack sizes are set up in start.S using the settings below
230 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
231 #ifdef CONFIG_USE_IRQ
232 #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
233 #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
236 /*-----------------------------------------------------------------------
237 * Physical Memory Map
239 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
240 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
241 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
242 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
244 /* SDRAM Bank Allocation method */
247 /*-----------------------------------------------------------------------
248 * FLASH and environment organization
251 /* **** PISMO SUPPORT *** */
253 /* Configure the PISMO */
254 #define PISMO1_NAND_SIZE GPMC_SIZE_128M
255 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M
257 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
259 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
260 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
262 #define CONFIG_SYS_FLASH_BASE boot_flash_base
264 /* Monitor at start of flash */
265 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
266 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
268 #define CONFIG_ENV_IS_IN_NAND 1
269 #define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */
270 #define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */
272 #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
273 #define CONFIG_ENV_OFFSET boot_flash_off
274 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
276 /*-----------------------------------------------------------------------
277 * CFI FLASH driver setup
279 /* timeout values are in ticks */
280 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
281 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
283 /* Flash banks JFFS2 should use */
284 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
285 CONFIG_SYS_MAX_NAND_DEVICE)
286 #define CONFIG_SYS_JFFS2_MEM_NAND
287 /* use flash_info[2] */
288 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
289 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
292 extern struct gpmc *gpmc_cfg;
293 extern unsigned int boot_flash_base;
294 extern volatile unsigned int boot_flash_env_addr;
295 extern unsigned int boot_flash_off;
296 extern unsigned int boot_flash_sec;
297 extern unsigned int boot_flash_type;
300 #endif /* __CONFIG_H */