include/configs/omap3_overo.h

   1 /*
   2  * Configuration settings for the Gumstix Overo board.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation; either version 2 of
   7  * the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17  * MA 02111-1307 USA
  18  */
  19
  20 #ifndef __CONFIG_H
  21 #define __CONFIG_H
  22 #include <asm/sizes.h>
  23
  24 /*
  25  * High Level Configuration Options
  26  */
  27 #define CONFIG_ARMCORTEXA8      1       /* This is an ARM V7 CPU core */
  28 #define CONFIG_OMAP             1       /* in a TI OMAP core */
  29 #define CONFIG_OMAP34XX         1       /* which is a 34XX */
  30 #define CONFIG_OMAP3430         1       /* which is in a 3430 */
  31 #define CONFIG_OMAP3_OVERO              1       /* working with overo */
  32
  33 #include <asm/arch/cpu.h>       /* get chip and board defs */
  34 #include <asm/arch/omap3.h>
  35
  36 /*
  37  * Display CPU and Board information
  38  */
  39 #define CONFIG_DISPLAY_CPUINFO          1
  40 #define CONFIG_DISPLAY_BOARDINFO        1
  41
  42 /* Clock Defines */
  43 #define V_OSCK                  26000000        /* Clock output from T2 */
  44 #define V_SCLK                  (V_OSCK >> 1)
  45
  46 #undef CONFIG_USE_IRQ           /* no support for IRQs */
  47 #define CONFIG_MISC_INIT_R
  48
  49 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
  50 #define CONFIG_SETUP_MEMORY_TAGS        1
  51 #define CONFIG_INITRD_TAG               1
  52 #define CONFIG_REVISION_TAG             1
  53
  54 /*
  55  * Size of malloc() pool
  56  */
  57 #define CONFIG_ENV_SIZE                 SZ_128K /* Total Size Environment */
  58                                                 /* Sector */
  59 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + SZ_128K)
  60 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* bytes reserved for */
  61                                                 /* initial data */
  62
  63 /*
  64  * Hardware drivers
  65  */
  66
  67 /*
  68  * NS16550 Configuration
  69  */
  70 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  71
  72 #define CONFIG_SYS_NS16550
  73 #define CONFIG_SYS_NS16550_SERIAL
  74 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  75 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  76
  77 /*
  78  * select serial console configuration
  79  */
  80 #define CONFIG_CONS_INDEX               3
  81 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  82 #define CONFIG_SERIAL3                  3
  83
  84 /* allow to overwrite serial and ethaddr */
  85 #define CONFIG_ENV_OVERWRITE
  86 #define CONFIG_BAUDRATE                 115200
  87 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600, \
  88                                         115200}
  89 #define CONFIG_MMC                      1
  90 #define CONFIG_OMAP3_MMC                1
  91 #define CONFIG_DOS_PARTITION            1
  92
  93 /* commands to include */
  94 #include <config_cmd_default.h>
  95
  96 #define CONFIG_CMD_EXT2         /* EXT2 Support                 */
  97 #define CONFIG_CMD_FAT          /* FAT support                  */
  98 #define CONFIG_CMD_JFFS2        /* JFFS2 Support                */
  99
 100 #define CONFIG_CMD_I2C          /* I2C serial bus support       */
 101 #define CONFIG_CMD_MMC          /* MMC support                  */
 102 #define CONFIG_CMD_NAND         /* NAND support                 */
 103
 104 #undef CONFIG_CMD_FLASH         /* flinfo, erase, protect       */
 105 #undef CONFIG_CMD_FPGA          /* FPGA configuration Support   */
 106 #undef CONFIG_CMD_IMI           /* iminfo                       */
 107 #undef CONFIG_CMD_IMLS          /* List all found images        */
 108 #undef CONFIG_CMD_NET           /* bootp, tftpboot, rarpboot    */
 109 #undef CONFIG_CMD_NFS           /* NFS support                  */
 110
 111 #define CONFIG_SYS_NO_FLASH
 112 #define CONFIG_SYS_I2C_SPEED            100000
 113 #define CONFIG_SYS_I2C_SLAVE            1
 114 #define CONFIG_SYS_I2C_BUS              0
 115 #define CONFIG_SYS_I2C_BUS_SELECT       1
 116 #define CONFIG_DRIVER_OMAP34XX_I2C      1
 117
 118 /*
 119  * Board NAND Info.
 120  */
 121 #define CONFIG_NAND_OMAP_GPMC
 122 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 123                                                         /* to access nand */
 124 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 125                                                         /* to access nand */
 126                                                         /* at CS0 */
 127 #define GPMC_NAND_ECC_LP_x16_LAYOUT     1
 128
 129 #define CONFIG_SYS_MAX_NAND_DEVICE      1       /* Max number of NAND */
 130                                                 /* devices */
 131 #define SECTORSIZE                      512
 132
 133 #define NAND_ALLOW_ERASE_ALL
 134 #define ADDR_COLUMN                     1
 135 #define ADDR_PAGE                       2
 136 #define ADDR_COLUMN_PAGE                3
 137
 138 #define NAND_ChipID_UNKNOWN             0x00
 139 #define NAND_MAX_FLOORS                 1
 140 #define NAND_MAX_CHIPS                  1
 141 #define NAND_NO_RB                      1
 142 #define CONFIG_SYS_NAND_WP
 143
 144 #define CONFIG_JFFS2_NAND
 145 /* nand device jffs2 lives on */
 146 #define CONFIG_JFFS2_DEV                "nand0"
 147 /* start of jffs2 partition */
 148 #define CONFIG_JFFS2_PART_OFFSET        0x680000
 149 #define CONFIG_JFFS2_PART_SIZE          0xf980000       /* size of jffs2 */
 150                                                         /* partition */
 151
 152 /* Environment information */
 153 #define CONFIG_BOOTDELAY                5
 154
 155 #define CONFIG_EXTRA_ENV_SETTINGS \
 156         "loadaddr=0x82000000\0" \
 157         "console=ttyS2,115200n8\0" \
 158         "videomode=1024x768@60,vxres=1024,vyres=768\0" \
 159         "videospec=omapfb:vram:2M,vram:4M\0" \
 160         "mmcargs=setenv bootargs console=${console} " \
 161                 "video=${videospec},mode:${videomode} " \
 162                 "root=/dev/mmcblk0p2 rw " \
 163                 "rootfstype=ext3 rootwait\0" \
 164         "nandargs=setenv bootargs console=${console} " \
 165                 "video=${videospec},mode:${videomode} " \
 166                 "root=/dev/mtdblock4 rw " \
 167                 "rootfstype=jffs2\0" \
 168         "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
 169         "bootscript=echo Running bootscript from mmc ...; " \
 170                 "source ${loadaddr}\0" \
 171         "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
 172         "mmcboot=echo Booting from mmc ...; " \
 173                 "run mmcargs; " \
 174                 "bootm ${loadaddr}\0" \
 175         "nandboot=echo Booting from nand ...; " \
 176                 "run nandargs; " \
 177                 "nand read ${loadaddr} 280000 400000; " \
 178                 "bootm ${loadaddr}\0" \
 179
 180 #define CONFIG_BOOTCOMMAND \
 181         "if mmc init; then " \
 182                 "if run loadbootscript; then " \
 183                         "run bootscript; " \
 184                 "else " \
 185                         "if run loaduimage; then " \
 186                                 "run mmcboot; " \
 187                         "else run nandboot; " \
 188                         "fi; " \
 189                 "fi; " \
 190         "else run nandboot; fi"
 191
 192 #define CONFIG_AUTO_COMPLETE    1
 193 /*
 194  * Miscellaneous configurable options
 195  */
 196 #define V_PROMPT                "Overo # "
 197
 198 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 199 #define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
 200 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 201 #define CONFIG_SYS_PROMPT               V_PROMPT
 202 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 203 /* Print Buffer Size */
 204 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 205                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 206 #define CONFIG_SYS_MAXARGS              16      /* max number of command */
 207                                                 /* args */
 208 /* Boot Argument Buffer Size */
 209 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 210 /* memtest works on */
 211 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)
 212 #define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 213                                         0x01F00000) /* 31MB */
 214
 215 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0) /* default load */
 216                                                                 /* address */
 217
 218 /*
 219  * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
 220  * 32KHz clk, or from external sig. This rate is divided by a local divisor.
 221  */
 222 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 223 #define CONFIG_SYS_PTV                  7       /* 2^(PTV+1) */
 224 #define CONFIG_SYS_HZ                   ((V_SCLK) / (2 << CONFIG_SYS_PTV))
 225
 226 /*-----------------------------------------------------------------------
 227  * Stack sizes
 228  *
 229  * The stack sizes are set up in start.S using the settings below
 230  */
 231 #define CONFIG_STACKSIZE        SZ_128K /* regular stack */
 232 #ifdef CONFIG_USE_IRQ
 233 #define CONFIG_STACKSIZE_IRQ    SZ_4K   /* IRQ stack */
 234 #define CONFIG_STACKSIZE_FIQ    SZ_4K   /* FIQ stack */
 235 #endif
 236
 237 /*-----------------------------------------------------------------------
 238  * Physical Memory Map
 239  */
 240 #define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
 241 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 242 #define PHYS_SDRAM_1_SIZE       SZ_32M  /* at least 32 meg */
 243 #define PHYS_SDRAM_2            OMAP34XX_SDRC_CS1
 244
 245 /* SDRAM Bank Allocation method */
 246 #define SDRC_R_B_C              1
 247
 248 /*-----------------------------------------------------------------------
 249  * FLASH and environment organization
 250  */
 251
 252 /* **** PISMO SUPPORT *** */
 253
 254 /* Configure the PISMO */
 255 #define PISMO1_NAND_SIZE                GPMC_SIZE_128M
 256 #define PISMO1_ONEN_SIZE                GPMC_SIZE_128M
 257
 258 #define CONFIG_SYS_MAX_FLASH_SECT       520     /* max number of sectors on */
 259                                                 /* one chip */
 260 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of flash banks */
 261 #define CONFIG_SYS_MONITOR_LEN          SZ_256K /* Reserve 2 sectors */
 262
 263 #define CONFIG_SYS_FLASH_BASE           boot_flash_base
 264
 265 /* Monitor at start of flash */
 266 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 267 #define CONFIG_SYS_ONENAND_BASE         ONENAND_MAP
 268
 269 #define CONFIG_ENV_IS_IN_NAND           1
 270 #define ONENAND_ENV_OFFSET              0x240000 /* environment starts here */
 271 #define SMNAND_ENV_OFFSET               0x240000 /* environment starts here */
 272
 273 #define CONFIG_SYS_ENV_SECT_SIZE        boot_flash_sec
 274 #define CONFIG_ENV_OFFSET               boot_flash_off
 275 #define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
 276
 277 /*-----------------------------------------------------------------------
 278  * CFI FLASH driver setup
 279  */
 280 /* timeout values are in ticks */
 281 #define CONFIG_SYS_FLASH_ERASE_TOUT     (100 * CONFIG_SYS_HZ)
 282 #define CONFIG_SYS_FLASH_WRITE_TOUT     (100 * CONFIG_SYS_HZ)
 283
 284 /* Flash banks JFFS2 should use */
 285 #define CONFIG_SYS_MAX_MTD_BANKS        (CONFIG_SYS_MAX_FLASH_BANKS + \
 286                                         CONFIG_SYS_MAX_NAND_DEVICE)
 287 #define CONFIG_SYS_JFFS2_MEM_NAND
 288 /* use flash_info[2] */
 289 #define CONFIG_SYS_JFFS2_FIRST_BANK     CONFIG_SYS_MAX_FLASH_BANKS
 290 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
 291
 292 #ifndef __ASSEMBLY__
 293 extern gpmc_csx_t *nand_cs_base;
 294 extern gpmc_t *gpmc_cfg_base;
 295 extern unsigned int boot_flash_base;
 296 extern volatile unsigned int boot_flash_env_addr;
 297 extern unsigned int boot_flash_off;
 298 extern unsigned int boot_flash_sec;
 299 extern unsigned int boot_flash_type;
 300 #endif
 301
 302
 303 #define WRITE_NAND_COMMAND(d, adr)\
 304                         writel(d, &nand_cs_base->nand_cmd)
 305 #define WRITE_NAND_ADDRESS(d, adr)\
 306                         writel(d, &nand_cs_base->nand_adr)
 307 #define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
 308 #define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
 309
 310 /* Other NAND Access APIs */
 311 #define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
 312                         while (0)
 313 #define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
 314                         while (0)
 315 #define NAND_DISABLE_CE(nand)
 316 #define NAND_ENABLE_CE(nand)
 317 #define NAND_WAIT_READY(nand)   udelay(10)
 318
 319 #endif                          /* __CONFIG_H */