include/configs/omap3_overo.h

   1 /*
   2  * Configuration settings for the Gumstix Overo board.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation; either version 2 of
   7  * the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17  * MA 02111-1307 USA
  18  */
  19
  20 #ifndef __CONFIG_H
  21 #define __CONFIG_H
  22
  23 /*
  24  * High Level Configuration Options
  25  */
  26 #define CONFIG_ARMV7            1       /* This is an ARM V7 CPU core */
  27 #define CONFIG_OMAP             1       /* in a TI OMAP core */
  28 #define CONFIG_OMAP34XX         1       /* which is a 34XX */
  29 #define CONFIG_OMAP3430         1       /* which is in a 3430 */
  30 #define CONFIG_OMAP3_OVERO      1       /* working with overo */
  31
  32 #define CONFIG_SDRC     /* The chip has SDRC controller */
  33
  34 #include <asm/arch/cpu.h>       /* get chip and board defs */
  35 #include <asm/arch/omap3.h>
  36
  37 /*
  38  * Display CPU and Board information
  39  */
  40 #define CONFIG_DISPLAY_CPUINFO          1
  41 #define CONFIG_DISPLAY_BOARDINFO        1
  42
  43 /* Clock Defines */
  44 #define V_OSCK                  26000000        /* Clock output from T2 */
  45 #define V_SCLK                  (V_OSCK >> 1)
  46
  47 #undef CONFIG_USE_IRQ           /* no support for IRQs */
  48 #define CONFIG_MISC_INIT_R
  49
  50 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
  51 #define CONFIG_SETUP_MEMORY_TAGS        1
  52 #define CONFIG_INITRD_TAG               1
  53 #define CONFIG_REVISION_TAG             1
  54
  55 /*
  56  * Size of malloc() pool
  57  */
  58 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB */
  59                                                 /* Sector */
  60 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (128 << 10))
  61 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* bytes reserved for */
  62                                                 /* initial data */
  63
  64 /*
  65  * Hardware drivers
  66  */
  67
  68 /*
  69  * NS16550 Configuration
  70  */
  71 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  72
  73 #define CONFIG_SYS_NS16550
  74 #define CONFIG_SYS_NS16550_SERIAL
  75 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  76 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  77
  78 /*
  79  * select serial console configuration
  80  */
  81 #define CONFIG_CONS_INDEX               3
  82 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  83 #define CONFIG_SERIAL3                  3
  84
  85 /* allow to overwrite serial and ethaddr */
  86 #define CONFIG_ENV_OVERWRITE
  87 #define CONFIG_BAUDRATE                 115200
  88 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600, \
  89                                         115200}
  90 #define CONFIG_GENERIC_MMC              1
  91 #define CONFIG_MMC                      1
  92 #define CONFIG_OMAP_HSMMC               1
  93 #define CONFIG_DOS_PARTITION            1
  94
  95 /* DDR - I use Micron DDR */
  96 #define CONFIG_OMAP3_MICRON_DDR         1
  97
  98 /* commands to include */
  99 #include <config_cmd_default.h>
 100
 101 #define CONFIG_CMD_EXT2         /* EXT2 Support                 */
 102 #define CONFIG_CMD_FAT          /* FAT support                  */
 103 #define CONFIG_CMD_JFFS2        /* JFFS2 Support                */
 104
 105 #define CONFIG_CMD_I2C          /* I2C serial bus support       */
 106 #define CONFIG_CMD_MMC          /* MMC support                  */
 107 #define CONFIG_CMD_NAND         /* NAND support                 */
 108
 109 #undef CONFIG_CMD_FLASH         /* flinfo, erase, protect       */
 110 #undef CONFIG_CMD_FPGA          /* FPGA configuration Support   */
 111 #undef CONFIG_CMD_IMI           /* iminfo                       */
 112 #undef CONFIG_CMD_IMLS          /* List all found images        */
 113 #undef CONFIG_CMD_NFS           /* NFS support                  */
 114 #define CONFIG_CMD_NET          /* bootp, tftpboot, rarpboot    */
 115
 116 #define CONFIG_SYS_NO_FLASH
 117 #define CONFIG_HARD_I2C                 1
 118 #define CONFIG_SYS_I2C_SPEED            100000
 119 #define CONFIG_SYS_I2C_SLAVE            1
 120 #define CONFIG_SYS_I2C_BUS              0
 121 #define CONFIG_SYS_I2C_BUS_SELECT       1
 122 #define CONFIG_DRIVER_OMAP34XX_I2C      1
 123
 124 /*
 125  * TWL4030
 126  */
 127 #define CONFIG_TWL4030_POWER            1
 128 #define CONFIG_TWL4030_LED              1
 129
 130 /*
 131  * Board NAND Info.
 132  */
 133 #define CONFIG_SYS_NAND_QUIET_TEST      1
 134 #define CONFIG_NAND_OMAP_GPMC
 135 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 136                                                         /* to access nand */
 137 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 138                                                         /* to access nand */
 139                                                         /* at CS0 */
 140 #define GPMC_NAND_ECC_LP_x16_LAYOUT     1
 141
 142 #define CONFIG_SYS_MAX_NAND_DEVICE      1       /* Max number of NAND */
 143                                                 /* devices */
 144 #define CONFIG_JFFS2_NAND
 145 /* nand device jffs2 lives on */
 146 #define CONFIG_JFFS2_DEV                "nand0"
 147 /* start of jffs2 partition */
 148 #define CONFIG_JFFS2_PART_OFFSET        0x680000
 149 #define CONFIG_JFFS2_PART_SIZE          0xf980000       /* size of jffs2 */
 150                                                         /* partition */
 151
 152 /* Environment information */
 153 #define CONFIG_BOOTDELAY                5
 154
 155 #define CONFIG_EXTRA_ENV_SETTINGS \
 156         "loadaddr=0x82000000\0" \
 157         "console=ttyS2,115200n8\0" \
 158         "mpurate=500\0" \
 159         "vram=12M\0" \
 160         "dvimode=1024x768MR-16@60\0" \
 161         "defaultdisplay=dvi\0" \
 162         "mmcdev=0\0" \
 163         "mmcroot=/dev/mmcblk0p2 rw\0" \
 164         "mmcrootfstype=ext3 rootwait\0" \
 165         "nandroot=/dev/mtdblock4 rw\0" \
 166         "nandrootfstype=jffs2\0" \
 167         "mmcargs=setenv bootargs console=${console} " \
 168                 "mpurate=${mpurate} " \
 169                 "vram=${vram} " \
 170                 "omapfb.mode=dvi:${dvimode} " \
 171                 "omapfb.debug=y " \
 172                 "omapdss.def_disp=${defaultdisplay} " \
 173                 "root=${mmcroot} " \
 174                 "rootfstype=${mmcrootfstype}\0" \
 175         "nandargs=setenv bootargs console=${console} " \
 176                 "mpurate=${mpurate} " \
 177                 "vram=${vram} " \
 178                 "omapfb.mode=dvi:${dvimode} " \
 179                 "omapfb.debug=y " \
 180                 "omapdss.def_disp=${defaultdisplay} " \
 181                 "root=${nandroot} " \
 182                 "rootfstype=${nandrootfstype}\0" \
 183         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 184         "bootscript=echo Running bootscript from mmc ...; " \
 185                 "source ${loadaddr}\0" \
 186         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 187         "mmcboot=echo Booting from mmc ...; " \
 188                 "run mmcargs; " \
 189                 "bootm ${loadaddr}\0" \
 190         "nandboot=echo Booting from nand ...; " \
 191                 "run nandargs; " \
 192                 "nand read ${loadaddr} 280000 400000; " \
 193                 "bootm ${loadaddr}\0" \
 194
 195 #define CONFIG_BOOTCOMMAND \
 196         "if mmc rescan ${mmcdev}; then " \
 197                 "if run loadbootscript; then " \
 198                         "run bootscript; " \
 199                 "else " \
 200                         "if run loaduimage; then " \
 201                                 "run mmcboot; " \
 202                         "else run nandboot; " \
 203                         "fi; " \
 204                 "fi; " \
 205         "else run nandboot; fi"
 206
 207 #define CONFIG_AUTO_COMPLETE    1
 208 /*
 209  * Miscellaneous configurable options
 210  */
 211 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 212 #define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
 213 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 214 #define CONFIG_SYS_PROMPT               "Overo # "
 215 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 216 /* Print Buffer Size */
 217 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 218                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 219 #define CONFIG_SYS_MAXARGS              16      /* max number of command */
 220                                                 /* args */
 221 /* Boot Argument Buffer Size */
 222 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 223 /* memtest works on */
 224 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)
 225 #define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 226                                         0x01F00000) /* 31MB */
 227
 228 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0) /* default load */
 229                                                                 /* address */
 230 /*
 231  * OMAP3 has 12 GP timers, they can be driven by the system clock
 232  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 233  * This rate is divided by a local divisor.
 234  */
 235 #define CONFIG_SYS_TIMERBASE            OMAP34XX_GPT2
 236 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 237 #define CONFIG_SYS_HZ                   1000
 238
 239 /*-----------------------------------------------------------------------
 240  * Stack sizes
 241  *
 242  * The stack sizes are set up in start.S using the settings below
 243  */
 244 #define CONFIG_STACKSIZE        (128 << 10)     /* regular stack 128 KiB */
 245 #ifdef CONFIG_USE_IRQ
 246 #define CONFIG_STACKSIZE_IRQ    (4 << 10)       /* IRQ stack 4 KiB */
 247 #define CONFIG_STACKSIZE_FIQ    (4 << 10)       /* FIQ stack 4 KiB */
 248 #endif
 249
 250 /*-----------------------------------------------------------------------
 251  * Physical Memory Map
 252  */
 253 #define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
 254 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 255 #define PHYS_SDRAM_1_SIZE       (32 << 20)      /* at least 32 MiB */
 256 #define PHYS_SDRAM_2            OMAP34XX_SDRC_CS1
 257
 258 /* SDRAM Bank Allocation method */
 259 #define SDRC_R_B_C              1
 260
 261 /*-----------------------------------------------------------------------
 262  * FLASH and environment organization
 263  */
 264
 265 /* **** PISMO SUPPORT *** */
 266
 267 /* Configure the PISMO */
 268 #define PISMO1_NAND_SIZE                GPMC_SIZE_128M
 269 #define PISMO1_ONEN_SIZE                GPMC_SIZE_128M
 270
 271 #define CONFIG_SYS_MAX_FLASH_SECT       520     /* max number of sectors on */
 272                                                 /* one chip */
 273 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of flash banks */
 274 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 275
 276 #define CONFIG_SYS_FLASH_BASE           boot_flash_base
 277
 278 /* Monitor at start of flash */
 279 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 280 #define CONFIG_SYS_ONENAND_BASE         ONENAND_MAP
 281
 282 #define CONFIG_ENV_IS_IN_NAND           1
 283 #define ONENAND_ENV_OFFSET              0x240000 /* environment starts here */
 284 #define SMNAND_ENV_OFFSET               0x240000 /* environment starts here */
 285
 286 #define CONFIG_SYS_ENV_SECT_SIZE        boot_flash_sec
 287 #define CONFIG_ENV_OFFSET               boot_flash_off
 288 #define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
 289
 290 /*-----------------------------------------------------------------------
 291  * CFI FLASH driver setup
 292  */
 293 /* timeout values are in ticks */
 294 #define CONFIG_SYS_FLASH_ERASE_TOUT     (100 * CONFIG_SYS_HZ)
 295 #define CONFIG_SYS_FLASH_WRITE_TOUT     (100 * CONFIG_SYS_HZ)
 296
 297 /* Flash banks JFFS2 should use */
 298 #define CONFIG_SYS_MAX_MTD_BANKS        (CONFIG_SYS_MAX_FLASH_BANKS + \
 299                                         CONFIG_SYS_MAX_NAND_DEVICE)
 300 #define CONFIG_SYS_JFFS2_MEM_NAND
 301 /* use flash_info[2] */
 302 #define CONFIG_SYS_JFFS2_FIRST_BANK     CONFIG_SYS_MAX_FLASH_BANKS
 303 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
 304
 305 #ifndef __ASSEMBLY__
 306 extern unsigned int boot_flash_base;
 307 extern volatile unsigned int boot_flash_env_addr;
 308 extern unsigned int boot_flash_off;
 309 extern unsigned int boot_flash_sec;
 310 extern unsigned int boot_flash_type;
 311 #endif
 312
 313 #if defined(CONFIG_CMD_NET)
 314 /*----------------------------------------------------------------------------
 315  * SMSC9211 Ethernet from SMSC9118 family
 316  *----------------------------------------------------------------------------
 317  */
 318
 319 #define CONFIG_NET_MULTI
 320 #define CONFIG_SMC911X          1
 321 #define CONFIG_SMC911X_32_BIT
 322 #define CONFIG_SMC911X_BASE     0x2C000000
 323
 324 #endif /* (CONFIG_CMD_NET) */
 325
 326 #endif                          /* __CONFIG_H */