2 * Common configuration settings for the TI OMAP3 EVM board.
4 * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __OMAP3_EVM_COMMON_H
10 #define __OMAP3_EVM_COMMON_H
13 * High level configuration options
15 #define CONFIG_OMAP /* This is TI OMAP core */
16 #define CONFIG_OMAP_GPIO
17 #define CONFIG_OMAP_COMMON
19 #define CONFIG_SDRC /* The chip has SDRC controller */
21 #define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */
22 #define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */
25 * Clock related definitions
27 #define V_OSCK 26000000 /* Clock output from T2 */
28 #define V_SCLK (V_OSCK >> 1)
31 * OMAP3 has 12 GP timers, they can be driven by the system clock
32 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
33 * This rate is divided by a local divisor.
35 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
36 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
38 /* Size of environment - 128KB */
39 #define CONFIG_ENV_SIZE (128 << 10)
41 /* Size of malloc pool */
42 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
46 * Note 1: CS1 may or may not be populated
47 * Note 2: SDRAM size is expected to be at least 32MB
49 #define CONFIG_NR_DRAM_BANKS 2
50 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
51 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
53 /* Limits for memtest */
54 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
55 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
56 0x01F00000) /* 31MB */
58 /* Default load address */
59 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
61 /* -----------------------------------------------------------------------------
63 * -----------------------------------------------------------------------------
67 * NS16550 Configuration
69 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
71 #define CONFIG_SYS_NS16550
72 #define CONFIG_SYS_NS16550_SERIAL
73 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
74 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
77 * select serial console configuration
79 #define CONFIG_CONS_INDEX 1
80 #define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */
81 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
82 #define CONFIG_BAUDRATE 115200
83 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
89 #define CONFIG_SYS_I2C
90 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
91 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
92 #define CONFIG_SYS_I2C_OMAP34XX
97 /* Monitor at start of flash - Reserve 2 sectors */
98 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
100 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
102 /* Start location & size of environment */
103 #define ONENAND_ENV_OFFSET 0x260000
104 #define SMNAND_ENV_OFFSET 0x260000
106 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
111 /* Physical address to access NAND */
112 #define CONFIG_SYS_NAND_ADDR NAND_BASE
114 /* Physical address to access NAND at CS0 */
115 #define CONFIG_SYS_NAND_BASE NAND_BASE
117 /* Max number of NAND devices */
118 #define CONFIG_SYS_MAX_NAND_DEVICE 1
119 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
120 /* Timeout values (in ticks) */
121 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
122 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
124 /* Flash banks JFFS2 should use */
125 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
126 CONFIG_SYS_MAX_NAND_DEVICE)
128 #define CONFIG_SYS_JFFS2_MEM_NAND
129 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
130 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
132 #define CONFIG_JFFS2_NAND
133 /* nand device jffs2 lives on */
134 #define CONFIG_JFFS2_DEV "nand0"
135 /* Start of jffs2 partition */
136 #define CONFIG_JFFS2_PART_OFFSET 0x680000
137 /* Size of jffs2 partition */
138 #define CONFIG_JFFS2_PART_SIZE 0xf980000
143 #ifdef CONFIG_USB_OMAP3
145 #ifdef CONFIG_MUSB_HCD
146 #define CONFIG_CMD_USB
148 #define CONFIG_USB_STORAGE
149 #define CONGIG_CMD_STORAGE
150 #define CONFIG_CMD_FAT
152 #ifdef CONFIG_USB_KEYBOARD
153 #define CONFIG_SYS_USB_EVENT_POLL
154 #define CONFIG_PREBOOT "usb start"
155 #endif /* CONFIG_USB_KEYBOARD */
157 #endif /* CONFIG_MUSB_HCD */
159 #ifdef CONFIG_MUSB_UDC
160 /* USB device configuration */
161 #define CONFIG_USB_DEVICE
162 #define CONFIG_USB_TTY
163 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
165 /* Change these to suit your needs */
166 #define CONFIG_USBD_VENDORID 0x0451
167 #define CONFIG_USBD_PRODUCTID 0x5678
168 #define CONFIG_USBD_MANUFACTURER "Texas Instruments"
169 #define CONFIG_USBD_PRODUCT_NAME "EVM"
170 #endif /* CONFIG_MUSB_UDC */
172 #endif /* CONFIG_USB_OMAP3 */
174 /* ----------------------------------------------------------------------------
176 * ----------------------------------------------------------------------------
178 #define CONFIG_SYS_PROMPT "OMAP3_EVM # "
179 #define CONFIG_SYS_MAXARGS 16 /* max args for a command */
181 #define CONFIG_MISC_INIT_R
183 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
184 #define CONFIG_SETUP_MEMORY_TAGS
185 #define CONFIG_INITRD_TAG
186 #define CONFIG_REVISION_TAG
188 /* Size of Console IO buffer */
189 #define CONFIG_SYS_CBSIZE 512
191 /* Size of print buffer */
192 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
193 sizeof(CONFIG_SYS_PROMPT) + 16)
195 /* Size of bootarg buffer */
196 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
198 #define CONFIG_BOOTFILE "uImage"
203 #if defined(CONFIG_CMD_NAND)
204 #define CONFIG_SYS_FLASH_BASE NAND_BASE
206 #define CONFIG_NAND_OMAP_GPMC
207 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
208 #elif defined(CONFIG_CMD_ONENAND)
209 #define CONFIG_SYS_FLASH_BASE ONENAND_MAP
210 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
213 #if !defined(CONFIG_ENV_IS_NOWHERE)
214 #if defined(CONFIG_CMD_NAND)
215 #define CONFIG_ENV_IS_IN_NAND
216 #elif defined(CONFIG_CMD_ONENAND)
217 #define CONFIG_ENV_IS_IN_ONENAND
218 #define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET
220 #endif /* CONFIG_ENV_IS_NOWHERE */
222 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
224 #if defined(CONFIG_CMD_NET)
226 /* Ethernet (SMSC9115 from SMSC9118 family) */
227 #define CONFIG_SMC911X
228 #define CONFIG_SMC911X_32_BIT
229 #define CONFIG_SMC911X_BASE 0x2C000000
232 #define CONFIG_BOOTP_SUBNETMASK 0x00000001
233 #define CONFIG_BOOTP_GATEWAY 0x00000002
234 #define CONFIG_BOOTP_HOSTNAME 0x00000004
235 #define CONFIG_BOOTP_BOOTPATH 0x00000010
237 #endif /* CONFIG_CMD_NET */
239 /* Support for relocation */
240 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
241 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
242 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
243 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
244 CONFIG_SYS_INIT_RAM_SIZE - \
245 GENERATED_GBL_DATA_SIZE)
247 /* -----------------------------------------------------------------------------
249 * -----------------------------------------------------------------------------
251 #define CONFIG_SYS_NO_FLASH
253 /* Uncomment to define the board revision statically */
254 /* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */
256 #define CONFIG_SYS_CACHELINE_SIZE 64
258 /* Defines for SPL */
259 #define CONFIG_SPL_FRAMEWORK
260 #define CONFIG_SPL_TEXT_BASE 0x40200800
261 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
262 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
264 #define CONFIG_SPL_BSS_START_ADDR 0x80000000
265 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
267 #define CONFIG_SPL_BOARD_INIT
268 #define CONFIG_SPL_LIBCOMMON_SUPPORT
269 #define CONFIG_SPL_LIBDISK_SUPPORT
270 #define CONFIG_SPL_I2C_SUPPORT
271 #define CONFIG_SPL_LIBGENERIC_SUPPORT
272 #define CONFIG_SPL_SERIAL_SUPPORT
273 #define CONFIG_SPL_POWER_SUPPORT
274 #define CONFIG_SPL_OMAP3_ID_NAND
275 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
278 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
279 * 64 bytes before this address should be set aside for u-boot.img's
280 * header. That is 0x800FFFC0--0x80100000 should not be used for any
283 #define CONFIG_SYS_TEXT_BASE 0x80100000
284 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
285 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
287 #endif /* __OMAP3_EVM_COMMON_H */