1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuration settings for the QUIPOS Cairo board.
5 * Copyright (C) DENX GmbH
8 * Albert ARIBAUD <albert.aribaud@3adev.fr>
10 * Derived from EVM code by
11 * Manikandan Pillai <mani.pillai@ti.com>
12 * Itself derived from Beagle Board and 3430 SDP code by
13 * Richard Woodruff <r-woodruff2@ti.com>
14 * Syed Mohammed Khasim <khasim@ti.com>
16 * Also derived from include/configs/omap3_beagle.h
19 #ifndef __OMAP3_CAIRO_CONFIG_H
20 #define __OMAP3_CAIRO_CONFIG_H
23 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
24 * 64 bytes before this address should be set aside for u-boot.img's
25 * header. That is 0x800FFFC0--0x80100000 should not be used for any
26 * other needs. We use this rather than the inherited defines from
27 * ti_armv7_common.h for backwards compatibility.
29 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
30 #define CONFIG_SPL_BSS_START_ADDR 0x80000000
31 #define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
32 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
33 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
35 #include <configs/ti_omap3_common.h>
37 #define CONFIG_MISC_INIT_R
39 #define CONFIG_REVISION_TAG 1
40 #define CONFIG_ENV_OVERWRITE
42 /* Enable Multi Bus support for I2C */
43 #define CONFIG_I2C_MULTI_BUS 1
45 /* Probe all devices */
46 #define CONFIG_SYS_I2C_NOPROBES { {0x0, 0x0} }
51 #define CONFIG_TWL4030_LED 1
56 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
58 #define CONFIG_EXTRA_ENV_SETTINGS \
60 "fdt_high=0x87000000\0" \
62 "fec_addr=00:50:C2:7E:90:F0\0" \
63 "netmask=255.255.255.0\0" \
64 "ipaddr=192.168.2.9\0" \
65 "gateway=192.168.2.1\0" \
66 "serverip=192.168.2.10\0" \
67 "nfshost=192.168.2.10\0" \
71 "bootargs_mmc_ramdisk=mem=128M " \
72 "console=ttyO1,115200n8 " \
73 "root=/dev/ram0 rw " \
74 "initrd=0x81600000,16M " \
75 "mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \
76 "omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \
77 "mmcboot=mmc init; " \
78 "fatload mmc 0 0x80000000 uImage; " \
79 "fatload mmc 0 0x81600000 ramdisk.gz; " \
80 "setenv bootargs ${bootargs_mmc_ramdisk}; " \
81 "bootm 0x80000000\0" \
82 "bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \
84 "nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \
85 "mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \
86 "omap_vout.vid1_static_vrfb_alloc=y\0" \
87 "boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \
88 "bootm 0x80000000\0" \
89 "bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \
90 "root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \
91 "omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \
92 "omapfb.rotate_type=1\0" \
93 "boot_nand=nand read.i 0x80000000 280000 300000; setenv " \
94 "bootargs ${bootargs_nand}; bootm 0x80000000\0" \
95 "ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
96 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
97 "i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
98 "ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
99 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
100 "mw 60 09 00 1; i2c mw 60 06 10 1\0" \
101 "ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
102 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
103 "i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
104 "ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
105 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
106 "i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \
107 "flash_xloader=mw.b 0x81600000 0xff 0x20000; " \
108 "nand erase 0 20000; " \
109 "fatload mmc 0 0x81600000 MLO; " \
111 "nand write.i 0x81600000 0 20000;\0" \
112 "flash_uboot=mw.b 0x81600000 0xff 0x40000; " \
113 "nand erase 80000 40000; " \
114 "fatload mmc 0 0x81600000 u-boot.bin; " \
116 "nand write.i 0x81600000 80000 40000;\0" \
117 "flash_kernel=mw.b 0x81600000 0xff 0x300000; " \
118 "nand erase 280000 300000; " \
119 "fatload mmc 0 0x81600000 uImage; " \
121 "nand write.i 0x81600000 280000 300000;\0" \
122 "flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \
124 "nand write.jffs2 0x680000 0xFF ${filesize}; " \
125 "nand erase 680000 ${filesize}; " \
126 "nand write.jffs2 81600000 680000 ${filesize};\0" \
127 "flash_scrub=nand scrub; " \
128 "run flash_xloader; " \
129 "run flash_uboot; " \
130 "run flash_kernel; " \
131 "run flash_rootfs;\0" \
132 "flash_all=run ledred; " \
133 "nand erase.chip; " \
135 "run flash_xloader; " \
136 "run flash_uboot; " \
137 "run flash_kernel; " \
138 "run flash_rootfs; " \
140 "run boot_nand; \0" \
142 #define CONFIG_BOOTCOMMAND \
143 "if fatload mmc 0 0x81600000 MLO; then run flash_all; " \
144 "else run boot_nand; fi"
147 * OMAP3 has 12 GP timers, they can be driven by the system clock
148 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
149 * This rate is divided by a local divisor.
151 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
153 /*-----------------------------------------------------------------------
154 * FLASH and environment organization
157 /* **** PISMO SUPPORT *** */
158 #if defined(CONFIG_CMD_NAND)
159 #define CONFIG_SYS_FLASH_BASE NAND_BASE
162 /* Monitor at start of flash */
163 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
164 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
166 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
167 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
169 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
170 #define CONFIG_ENV_OFFSET 0x260000
171 #define CONFIG_ENV_ADDR 0x260000
173 /* Defines for SPL */
175 /* NAND boot config */
176 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
177 #define CONFIG_SYS_NAND_PAGE_COUNT 64
178 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
179 #define CONFIG_SYS_NAND_OOBSIZE 64
180 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
181 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
182 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
184 #define CONFIG_SYS_NAND_ECCSIZE 512
185 #define CONFIG_SYS_NAND_ECCBYTES 3
186 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
187 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
188 /* NAND: SPL falcon mode configs */
189 #ifdef CONFIG_SPL_OS_BOOT
190 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
194 #define CONFIG_BOOTFILE "uImage"
196 /* Override OMAP3 common serial console configuration from UART3
199 * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3)
200 * are needed and peripheral clocks for UART2 must be enabled in
201 * function per_clocks_enable().
203 #ifdef CONFIG_SPL_BUILD
204 #undef CONFIG_SERIAL3
205 #define CONFIG_SERIAL2
208 /* Provide the MACH_TYPE value the vendor kernel requires */
209 #define CONFIG_MACH_TYPE 3063
211 /*-----------------------------------------------------------------------
212 * FLASH and environment organization
215 /* **** PISMO SUPPORT *** */
217 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
219 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
221 /*-----------------------------------------------------------------------
222 * CFI FLASH driver setup
224 /* timeout values are in ticks */
225 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
226 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
228 /* Flash banks JFFS2 should use */
229 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
230 CONFIG_SYS_MAX_NAND_DEVICE)
231 #define CONFIG_SYS_JFFS2_MEM_NAND
232 /* use flash_info[2] */
233 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
234 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
236 #endif /* __OMAP3_CAIRO_CONFIG_H */