1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuration settings for the QUIPOS Cairo board.
5 * Copyright (C) DENX GmbH
8 * Albert ARIBAUD <albert.aribaud@3adev.fr>
10 * Derived from EVM code by
11 * Manikandan Pillai <mani.pillai@ti.com>
12 * Itself derived from Beagle Board and 3430 SDP code by
13 * Richard Woodruff <r-woodruff2@ti.com>
14 * Syed Mohammed Khasim <khasim@ti.com>
16 * Also derived from include/configs/omap3_beagle.h
19 #ifndef __OMAP3_CAIRO_CONFIG_H
20 #define __OMAP3_CAIRO_CONFIG_H
22 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
25 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
26 * 64 bytes before this address should be set aside for u-boot.img's
27 * header. That is 0x800FFFC0--0x80100000 should not be used for any
28 * other needs. We use this rather than the inherited defines from
29 * ti_armv7_common.h for backwards compatibility.
31 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
32 #define CONFIG_SPL_BSS_START_ADDR 0x80000000
33 #define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
34 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
35 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
37 #include <configs/ti_omap3_common.h>
39 #define CONFIG_MISC_INIT_R
41 #define CONFIG_REVISION_TAG 1
42 #define CONFIG_ENV_OVERWRITE
44 /* Enable Multi Bus support for I2C */
45 #define CONFIG_I2C_MULTI_BUS 1
47 /* Probe all devices */
48 #define CONFIG_SYS_I2C_NOPROBES { {0x0, 0x0} }
53 #define CONFIG_TWL4030_LED 1
58 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
60 #define CONFIG_EXTRA_ENV_SETTINGS \
62 "fdt_high=0x87000000\0" \
64 "fec_addr=00:50:C2:7E:90:F0\0" \
65 "netmask=255.255.255.0\0" \
66 "ipaddr=192.168.2.9\0" \
67 "gateway=192.168.2.1\0" \
68 "serverip=192.168.2.10\0" \
69 "nfshost=192.168.2.10\0" \
73 "bootargs_mmc_ramdisk=mem=128M " \
74 "console=ttyO1,115200n8 " \
75 "root=/dev/ram0 rw " \
76 "initrd=0x81600000,16M " \
77 "mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \
78 "omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \
79 "mmcboot=mmc init; " \
80 "fatload mmc 0 0x80000000 uImage; " \
81 "fatload mmc 0 0x81600000 ramdisk.gz; " \
82 "setenv bootargs ${bootargs_mmc_ramdisk}; " \
83 "bootm 0x80000000\0" \
84 "bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \
86 "nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \
87 "mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \
88 "omap_vout.vid1_static_vrfb_alloc=y\0" \
89 "boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \
90 "bootm 0x80000000\0" \
91 "bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \
92 "root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \
93 "omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \
94 "omapfb.rotate_type=1\0" \
95 "boot_nand=nand read.i 0x80000000 280000 300000; setenv " \
96 "bootargs ${bootargs_nand}; bootm 0x80000000\0" \
97 "ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
98 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
99 "i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
100 "ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
101 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
102 "mw 60 09 00 1; i2c mw 60 06 10 1\0" \
103 "ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
104 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
105 "i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
106 "ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
107 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
108 "i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \
109 "flash_xloader=mw.b 0x81600000 0xff 0x20000; " \
110 "nand erase 0 20000; " \
111 "fatload mmc 0 0x81600000 MLO; " \
113 "nand write.i 0x81600000 0 20000;\0" \
114 "flash_uboot=mw.b 0x81600000 0xff 0x40000; " \
115 "nand erase 80000 40000; " \
116 "fatload mmc 0 0x81600000 u-boot.bin; " \
118 "nand write.i 0x81600000 80000 40000;\0" \
119 "flash_kernel=mw.b 0x81600000 0xff 0x300000; " \
120 "nand erase 280000 300000; " \
121 "fatload mmc 0 0x81600000 uImage; " \
123 "nand write.i 0x81600000 280000 300000;\0" \
124 "flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \
126 "nand write.jffs2 0x680000 0xFF ${filesize}; " \
127 "nand erase 680000 ${filesize}; " \
128 "nand write.jffs2 81600000 680000 ${filesize};\0" \
129 "flash_scrub=nand scrub; " \
130 "run flash_xloader; " \
131 "run flash_uboot; " \
132 "run flash_kernel; " \
133 "run flash_rootfs;\0" \
134 "flash_all=run ledred; " \
135 "nand erase.chip; " \
137 "run flash_xloader; " \
138 "run flash_uboot; " \
139 "run flash_kernel; " \
140 "run flash_rootfs; " \
142 "run boot_nand; \0" \
144 #define CONFIG_BOOTCOMMAND \
145 "if fatload mmc 0 0x81600000 MLO; then run flash_all; " \
146 "else run boot_nand; fi"
149 * OMAP3 has 12 GP timers, they can be driven by the system clock
150 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
151 * This rate is divided by a local divisor.
153 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
155 /*-----------------------------------------------------------------------
156 * FLASH and environment organization
159 /* **** PISMO SUPPORT *** */
160 #if defined(CONFIG_CMD_NAND)
161 #define CONFIG_SYS_FLASH_BASE NAND_BASE
164 /* Monitor at start of flash */
165 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
166 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
168 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
169 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
171 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
172 #define CONFIG_ENV_OFFSET 0x260000
173 #define CONFIG_ENV_ADDR 0x260000
175 /* Defines for SPL */
177 /* NAND boot config */
178 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
179 #define CONFIG_SYS_NAND_PAGE_COUNT 64
180 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
181 #define CONFIG_SYS_NAND_OOBSIZE 64
182 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
183 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
184 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
186 #define CONFIG_SYS_NAND_ECCSIZE 512
187 #define CONFIG_SYS_NAND_ECCBYTES 3
188 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
189 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
190 /* NAND: SPL falcon mode configs */
191 #ifdef CONFIG_SPL_OS_BOOT
192 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
196 #define CONFIG_BOOTFILE "uImage"
198 /* Override OMAP3 common serial console configuration from UART3
201 * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3)
202 * are needed and peripheral clocks for UART2 must be enabled in
203 * function per_clocks_enable().
205 #ifdef CONFIG_SPL_BUILD
206 #undef CONFIG_SYS_NS16550_COM3
207 #define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2
208 #undef CONFIG_SERIAL3
209 #define CONFIG_SERIAL2
212 /* Provide the MACH_TYPE value the vendor kernel requires */
213 #define CONFIG_MACH_TYPE 3063
215 /*-----------------------------------------------------------------------
216 * FLASH and environment organization
219 /* **** PISMO SUPPORT *** */
221 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
223 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
225 /*-----------------------------------------------------------------------
226 * CFI FLASH driver setup
228 /* timeout values are in ticks */
229 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
230 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
232 /* Flash banks JFFS2 should use */
233 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
234 CONFIG_SYS_MAX_NAND_DEVICE)
235 #define CONFIG_SYS_JFFS2_MEM_NAND
236 /* use flash_info[2] */
237 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
238 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
240 #endif /* __OMAP3_CAIRO_CONFIG_H */