2 * (C) Copyright 2006-2008
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
7 * Configuration settings for the TI OMAP3530 Beagle board.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * High Level Configuration Options
34 #define CONFIG_OMAP 1 /* in a TI OMAP core */
35 #define CONFIG_OMAP34XX 1 /* which is a 34XX */
36 #define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */
37 #define CONFIG_OMAP_GPIO
39 #define CONFIG_SDRC /* The chip has SDRC controller */
41 #include <asm/arch/cpu.h> /* get chip and board defs */
42 #include <asm/arch/omap3.h>
45 * Display CPU and Board information
47 #define CONFIG_DISPLAY_CPUINFO 1
48 #define CONFIG_DISPLAY_BOARDINFO 1
51 #define V_OSCK 26000000 /* Clock output from T2 */
52 #define V_SCLK (V_OSCK >> 1)
54 #define CONFIG_MISC_INIT_R
56 #define CONFIG_OF_LIBFDT 1
58 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
59 #define CONFIG_SETUP_MEMORY_TAGS 1
60 #define CONFIG_INITRD_TAG 1
61 #define CONFIG_REVISION_TAG 1
64 * Size of malloc() pool
66 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
68 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
75 * NS16550 Configuration
77 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
79 #define CONFIG_SYS_NS16550
80 #define CONFIG_SYS_NS16550_SERIAL
81 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
82 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
85 * select serial console configuration
87 #define CONFIG_CONS_INDEX 3
88 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
89 #define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */
91 /* allow to overwrite serial and ethaddr */
92 #define CONFIG_ENV_OVERWRITE
93 #define CONFIG_BAUDRATE 115200
94 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
96 #define CONFIG_GENERIC_MMC 1
98 #define CONFIG_OMAP_HSMMC 1
99 #define CONFIG_DOS_PARTITION 1
102 #define CONFIG_STATUS_LED 1
103 #define CONFIG_BOARD_SPECIFIC_LED 1
104 #define STATUS_LED_BIT 0x01
105 #define STATUS_LED_STATE STATUS_LED_ON
106 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
107 #define STATUS_LED_BIT1 0x02
108 #define STATUS_LED_STATE1 STATUS_LED_ON
109 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
110 #define STATUS_LED_BOOT STATUS_LED_BIT
111 #define STATUS_LED_GREEN STATUS_LED_BIT1
113 /* Enable Multi Bus support for I2C */
114 #define CONFIG_I2C_MULTI_BUS 1
116 /* Probe all devices */
117 #define CONFIG_SYS_I2C_NOPROBES {{0x0, 0x0}}
120 #define CONFIG_MUSB_GADGET
121 #define CONFIG_USB_MUSB_OMAP2PLUS
122 #define CONFIG_MUSB_PIO_ONLY
123 #define CONFIG_USB_GADGET_DUALSPEED
124 #define CONFIG_TWL4030_USB 1
125 #define CONFIG_USB_ETHER
126 #define CONFIG_USB_ETHER_RNDIS
129 #define CONFIG_CMD_USB
130 #define CONFIG_USB_EHCI
132 #define CONFIG_USB_EHCI_OMAP
133 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147
135 #define CONFIG_USB_ULPI
136 #define CONFIG_USB_ULPI_VIEWPORT_OMAP
138 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
139 #define CONFIG_USB_HOST_ETHER
140 #define CONFIG_USB_ETHER_SMSC95XX
141 #define CONFIG_USB_ETHER_ASIX
144 /* commands to include */
145 #include <config_cmd_default.h>
147 #define CONFIG_CMD_ASKENV
149 #define CONFIG_CMD_CACHE
150 #define CONFIG_CMD_EXT2 /* EXT2 Support */
151 #define CONFIG_CMD_FAT /* FAT support */
152 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
153 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
154 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
155 #define MTDIDS_DEFAULT "nand0=nand"
156 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
157 "1920k(u-boot),128k(u-boot-env),"\
160 #define CONFIG_CMD_I2C /* I2C serial bus support */
161 #define CONFIG_CMD_MMC /* MMC support */
162 #define CONFIG_USB_STORAGE /* USB storage support */
163 #define CONFIG_CMD_NAND /* NAND support */
164 #define CONFIG_CMD_LED /* LED support */
165 #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
166 #define CONFIG_CMD_NFS /* NFS support */
167 #define CONFIG_CMD_PING
168 #define CONFIG_CMD_DHCP
169 #define CONFIG_CMD_SETEXPR /* Evaluate expressions */
170 #define CONFIG_CMD_GPIO /* Enable gpio command */
172 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
173 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
174 #undef CONFIG_CMD_IMI /* iminfo */
175 #undef CONFIG_CMD_IMLS /* List all found images */
177 #define CONFIG_SYS_NO_FLASH
178 #define CONFIG_HARD_I2C 1
179 #define CONFIG_SYS_I2C_SPEED 100000
180 #define CONFIG_SYS_I2C_SLAVE 1
181 #define CONFIG_SYS_I2C_BUS 0
182 #define CONFIG_SYS_I2C_BUS_SELECT 1
183 #define CONFIG_I2C_MULTI_BUS 1
184 #define CONFIG_DRIVER_OMAP34XX_I2C 1
185 #define CONFIG_VIDEO_OMAP3 /* DSS Support */
190 #define CONFIG_TWL4030_POWER 1
191 #define CONFIG_TWL4030_LED 1
196 #define CONFIG_SYS_NAND_QUIET_TEST 1
197 #define CONFIG_NAND_OMAP_GPMC
198 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
200 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
201 /* to access nand at */
203 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1
205 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
207 #define CONFIG_JFFS2_NAND
208 /* nand device jffs2 lives on */
209 #define CONFIG_JFFS2_DEV "nand0"
210 /* start of jffs2 partition */
211 #define CONFIG_JFFS2_PART_OFFSET 0x680000
212 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
215 /* Environment information */
216 #define CONFIG_BOOTDELAY 3
218 #define CONFIG_EXTRA_ENV_SETTINGS \
219 "loadaddr=0x80200000\0" \
220 "rdaddr=0x81000000\0" \
222 "bootfile=uImage.beagle\0" \
223 "console=ttyO2,115200n8\0" \
229 "dvimode=640x480MR-16@60\0" \
230 "defaultdisplay=dvi\0" \
232 "mmcroot=/dev/mmcblk0p2 rw\0" \
233 "mmcrootfstype=ext3 rootwait\0" \
234 "nandroot=ubi0:rootfs ubi.mtd=4\0" \
235 "nandrootfstype=ubifs\0" \
236 "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \
237 "ramrootfstype=ext2\0" \
238 "mmcargs=setenv bootargs console=${console} " \
240 "mpurate=${mpurate} " \
244 "omapfb.mode=dvi:${dvimode} " \
245 "omapdss.def_disp=${defaultdisplay} " \
247 "rootfstype=${mmcrootfstype}\0" \
248 "nandargs=setenv bootargs console=${console} " \
250 "mpurate=${mpurate} " \
254 "omapfb.mode=dvi:${dvimode} " \
255 "omapdss.def_disp=${defaultdisplay} " \
256 "root=${nandroot} " \
257 "rootfstype=${nandrootfstype}\0" \
258 "bootenv=uEnv.txt\0" \
259 "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
260 "importbootenv=echo Importing environment from mmc ...; " \
261 "env import -t $loadaddr $filesize\0" \
262 "ramargs=setenv bootargs console=${console} " \
264 "mpurate=${mpurate} " \
267 "omapfb.mode=dvi:${dvimode} " \
268 "omapdss.def_disp=${defaultdisplay} " \
270 "rootfstype=${ramrootfstype}\0" \
271 "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
272 "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
273 "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} /boot/uImage\0" \
274 "mmcboot=echo Booting from mmc ...; " \
276 "bootm ${loadaddr}\0" \
277 "nandboot=echo Booting from nand ...; " \
279 "nand read ${loadaddr} 280000 400000; " \
280 "bootm ${loadaddr}\0" \
281 "ramboot=echo Booting from ramdisk ...; " \
283 "bootm ${loadaddr}\0" \
284 "userbutton=if gpio input 173; then run userbutton_xm; " \
285 "else run userbutton_nonxm; fi;\0" \
286 "userbutton_xm=gpio input 4;\0" \
287 "userbutton_nonxm=gpio input 7;\0"
288 /* "run userbutton" will return 1 (false) if is pressed and 0 (false) if not */
289 #define CONFIG_BOOTCOMMAND \
290 "mmc dev ${mmcdev}; if mmc rescan; then " \
291 "if run userbutton; then " \
292 "setenv bootenv uEnv.txt;" \
294 "setenv bootenv user.txt;" \
296 "echo SD/MMC found on device ${mmcdev};" \
297 "if run loadbootenv; then " \
298 "echo Loaded environment from ${bootenv};" \
299 "run importbootenv;" \
301 "if test -n $uenvcmd; then " \
302 "echo Running uenvcmd ...;" \
305 "if run loaduimage; then " \
311 #define CONFIG_AUTO_COMPLETE 1
313 * Miscellaneous configurable options
315 #define CONFIG_SYS_LONGHELP /* undef to save memory */
316 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
317 #define CONFIG_SYS_PROMPT "OMAP3 beagleboard.org # "
318 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
319 /* Print Buffer Size */
320 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
321 sizeof(CONFIG_SYS_PROMPT) + 16)
322 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
323 /* Boot Argument Buffer Size */
324 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
326 #define CONFIG_SYS_ALT_MEMTEST 1
327 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */
329 #define CONFIG_SYS_MEMTEST_END (0x87FFFFFF) /* 128MB */
330 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
332 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
336 * OMAP3 has 12 GP timers, they can be driven by the system clock
337 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
338 * This rate is divided by a local divisor.
340 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
341 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
342 #define CONFIG_SYS_HZ 1000
344 /*-----------------------------------------------------------------------
345 * Physical Memory Map
347 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
348 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
349 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
351 /*-----------------------------------------------------------------------
352 * FLASH and environment organization
355 /* **** PISMO SUPPORT *** */
357 /* Configure the PISMO */
358 #define PISMO1_NAND_SIZE GPMC_SIZE_128M
359 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M
361 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
363 #if defined(CONFIG_CMD_NAND)
364 #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
367 /* Monitor at start of flash */
368 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
369 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
371 #define CONFIG_ENV_IS_IN_NAND 1
372 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
373 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
375 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
376 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
377 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
379 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
380 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
381 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
382 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
383 CONFIG_SYS_INIT_RAM_SIZE - \
384 GENERATED_GBL_DATA_SIZE)
386 #define CONFIG_OMAP3_SPI
388 #define CONFIG_SYS_CACHELINE_SIZE 64
390 /* Defines for SPL */
392 #define CONFIG_SPL_FRAMEWORK
393 #define CONFIG_SPL_NAND_SIMPLE
394 #define CONFIG_SPL_TEXT_BASE 0x40200800
395 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
396 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
398 #define CONFIG_SPL_BSS_START_ADDR 0x80000000
399 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
401 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
402 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
403 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
404 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
406 #define CONFIG_SPL_BOARD_INIT
407 #define CONFIG_SPL_LIBCOMMON_SUPPORT
408 #define CONFIG_SPL_LIBDISK_SUPPORT
409 #define CONFIG_SPL_I2C_SUPPORT
410 #define CONFIG_SPL_LIBGENERIC_SUPPORT
411 #define CONFIG_SPL_MMC_SUPPORT
412 #define CONFIG_SPL_FAT_SUPPORT
413 #define CONFIG_SPL_SERIAL_SUPPORT
414 #define CONFIG_SPL_NAND_SUPPORT
415 #define CONFIG_SPL_NAND_BASE
416 #define CONFIG_SPL_NAND_DRIVERS
417 #define CONFIG_SPL_NAND_ECC
418 #define CONFIG_SPL_GPIO_SUPPORT
419 #define CONFIG_SPL_POWER_SUPPORT
420 #define CONFIG_SPL_OMAP3_ID_NAND
421 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
423 /* NAND boot config */
424 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
425 #define CONFIG_SYS_NAND_PAGE_COUNT 64
426 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
427 #define CONFIG_SYS_NAND_OOBSIZE 64
428 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
429 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
430 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
432 #define CONFIG_SYS_NAND_ECCSIZE 512
433 #define CONFIG_SYS_NAND_ECCBYTES 3
434 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
435 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
438 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
439 * 64 bytes before this address should be set aside for u-boot.img's
440 * header. That is 0x800FFFC0--0x80100000 should not be used for any
443 #define CONFIG_SYS_TEXT_BASE 0x80100000
444 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
445 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
447 #endif /* __CONFIG_H */