2 * (C) Copyright 2006-2008
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
7 * Configuration settings for the TI OMAP3530 Beagle board.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * High Level Configuration Options
34 #define CONFIG_OMAP 1 /* in a TI OMAP core */
35 #define CONFIG_OMAP34XX 1 /* which is a 34XX */
36 #define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */
37 #define CONFIG_OMAP_GPIO
39 #define CONFIG_SDRC /* The chip has SDRC controller */
41 #include <asm/arch/cpu.h> /* get chip and board defs */
42 #include <asm/arch/omap3.h>
45 * Display CPU and Board information
47 #define CONFIG_DISPLAY_CPUINFO 1
48 #define CONFIG_DISPLAY_BOARDINFO 1
51 #define V_OSCK 26000000 /* Clock output from T2 */
52 #define V_SCLK (V_OSCK >> 1)
54 #define CONFIG_MISC_INIT_R
56 #define CONFIG_OF_LIBFDT
57 #define CONFIG_CMD_BOOTZ
59 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
60 #define CONFIG_SETUP_MEMORY_TAGS 1
61 #define CONFIG_INITRD_TAG 1
62 #define CONFIG_REVISION_TAG 1
65 * Size of malloc() pool
67 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
69 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
76 * NS16550 Configuration
78 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
80 #define CONFIG_SYS_NS16550
81 #define CONFIG_SYS_NS16550_SERIAL
82 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
83 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
86 * select serial console configuration
88 #define CONFIG_CONS_INDEX 3
89 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
90 #define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */
92 /* allow to overwrite serial and ethaddr */
93 #define CONFIG_ENV_OVERWRITE
94 #define CONFIG_BAUDRATE 115200
95 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
97 #define CONFIG_GENERIC_MMC 1
99 #define CONFIG_OMAP_HSMMC 1
100 #define CONFIG_DOS_PARTITION 1
103 #define CONFIG_STATUS_LED 1
104 #define CONFIG_BOARD_SPECIFIC_LED 1
105 #define STATUS_LED_BIT 0x01
106 #define STATUS_LED_STATE STATUS_LED_ON
107 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
108 #define STATUS_LED_BIT1 0x02
109 #define STATUS_LED_STATE1 STATUS_LED_ON
110 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
111 #define STATUS_LED_BOOT STATUS_LED_BIT
112 #define STATUS_LED_GREEN STATUS_LED_BIT1
114 /* Enable Multi Bus support for I2C */
115 #define CONFIG_I2C_MULTI_BUS 1
117 /* Probe all devices */
118 #define CONFIG_SYS_I2C_NOPROBES {{0x0, 0x0}}
121 #define CONFIG_MUSB_GADGET
122 #define CONFIG_USB_MUSB_OMAP2PLUS
123 #define CONFIG_MUSB_PIO_ONLY
124 #define CONFIG_USB_GADGET_DUALSPEED
125 #define CONFIG_TWL4030_USB 1
126 #define CONFIG_USB_ETHER
127 #define CONFIG_USB_ETHER_RNDIS
130 #define CONFIG_CMD_USB
131 #define CONFIG_USB_EHCI
133 #define CONFIG_USB_EHCI_OMAP
134 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147
136 #define CONFIG_USB_ULPI
137 #define CONFIG_USB_ULPI_VIEWPORT_OMAP
139 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
140 #define CONFIG_USB_HOST_ETHER
141 #define CONFIG_USB_ETHER_SMSC95XX
142 #define CONFIG_USB_ETHER_ASIX
145 /* commands to include */
146 #include <config_cmd_default.h>
148 #define CONFIG_CMD_ASKENV
150 #define CONFIG_CMD_CACHE
151 #define CONFIG_CMD_EXT2 /* EXT2 Support */
152 #define CONFIG_CMD_FAT /* FAT support */
153 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
154 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
155 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
156 #define MTDIDS_DEFAULT "nand0=nand"
157 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
158 "1920k(u-boot),128k(u-boot-env),"\
161 #define CONFIG_CMD_I2C /* I2C serial bus support */
162 #define CONFIG_CMD_MMC /* MMC support */
163 #define CONFIG_USB_STORAGE /* USB storage support */
164 #define CONFIG_CMD_NAND /* NAND support */
165 #define CONFIG_CMD_LED /* LED support */
166 #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
167 #define CONFIG_CMD_NFS /* NFS support */
168 #define CONFIG_CMD_PING
169 #define CONFIG_CMD_DHCP
170 #define CONFIG_CMD_SETEXPR /* Evaluate expressions */
171 #define CONFIG_CMD_GPIO /* Enable gpio command */
173 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
174 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
175 #undef CONFIG_CMD_IMI /* iminfo */
176 #undef CONFIG_CMD_IMLS /* List all found images */
178 #define CONFIG_SYS_NO_FLASH
179 #define CONFIG_HARD_I2C 1
180 #define CONFIG_SYS_I2C_SPEED 100000
181 #define CONFIG_SYS_I2C_SLAVE 1
182 #define CONFIG_I2C_MULTI_BUS 1
183 #define CONFIG_DRIVER_OMAP34XX_I2C 1
184 #define CONFIG_VIDEO_OMAP3 /* DSS Support */
189 #define CONFIG_TWL4030_POWER 1
190 #define CONFIG_TWL4030_LED 1
195 #define CONFIG_SYS_NAND_QUIET_TEST 1
196 #define CONFIG_NAND_OMAP_GPMC
197 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
199 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
200 /* to access nand at */
202 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1
204 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
206 #define CONFIG_JFFS2_NAND
207 /* nand device jffs2 lives on */
208 #define CONFIG_JFFS2_DEV "nand0"
209 /* start of jffs2 partition */
210 #define CONFIG_JFFS2_PART_OFFSET 0x680000
211 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
214 /* Environment information */
215 #define CONFIG_BOOTDELAY 3
217 #define CONFIG_EXTRA_ENV_SETTINGS \
218 "loadaddr=0x80200000\0" \
219 "rdaddr=0x81000000\0" \
221 "bootfile=uImage.beagle\0" \
222 "console=ttyO2,115200n8\0" \
228 "dvimode=640x480MR-16@60\0" \
229 "defaultdisplay=dvi\0" \
231 "mmcroot=/dev/mmcblk0p2 rw\0" \
232 "mmcrootfstype=ext3 rootwait\0" \
233 "nandroot=ubi0:rootfs ubi.mtd=4\0" \
234 "nandrootfstype=ubifs\0" \
235 "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \
236 "ramrootfstype=ext2\0" \
237 "mmcargs=setenv bootargs console=${console} " \
239 "mpurate=${mpurate} " \
243 "omapfb.mode=dvi:${dvimode} " \
244 "omapdss.def_disp=${defaultdisplay} " \
246 "rootfstype=${mmcrootfstype}\0" \
247 "nandargs=setenv bootargs console=${console} " \
249 "mpurate=${mpurate} " \
253 "omapfb.mode=dvi:${dvimode} " \
254 "omapdss.def_disp=${defaultdisplay} " \
255 "root=${nandroot} " \
256 "rootfstype=${nandrootfstype}\0" \
257 "bootenv=uEnv.txt\0" \
258 "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
259 "importbootenv=echo Importing environment from mmc ...; " \
260 "env import -t $loadaddr $filesize\0" \
261 "ramargs=setenv bootargs console=${console} " \
263 "mpurate=${mpurate} " \
266 "omapfb.mode=dvi:${dvimode} " \
267 "omapdss.def_disp=${defaultdisplay} " \
269 "rootfstype=${ramrootfstype}\0" \
270 "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
271 "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
272 "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} /boot/uImage\0" \
273 "mmcboot=echo Booting from mmc ...; " \
275 "bootm ${loadaddr}\0" \
276 "nandboot=echo Booting from nand ...; " \
278 "nand read ${loadaddr} 280000 400000; " \
279 "bootm ${loadaddr}\0" \
280 "ramboot=echo Booting from ramdisk ...; " \
282 "bootm ${loadaddr}\0" \
283 "userbutton=if gpio input 173; then run userbutton_xm; " \
284 "else run userbutton_nonxm; fi;\0" \
285 "userbutton_xm=gpio input 4;\0" \
286 "userbutton_nonxm=gpio input 7;\0"
287 /* "run userbutton" will return 1 (false) if pressed and 0 (true) if not */
288 #define CONFIG_BOOTCOMMAND \
289 "mmc dev ${mmcdev}; if mmc rescan; then " \
290 "if run userbutton; then " \
291 "setenv bootenv uEnv.txt;" \
293 "setenv bootenv user.txt;" \
295 "echo SD/MMC found on device ${mmcdev};" \
296 "if run loadbootenv; then " \
297 "echo Loaded environment from ${bootenv};" \
298 "run importbootenv;" \
300 "if test -n $uenvcmd; then " \
301 "echo Running uenvcmd ...;" \
304 "if run loaduimage; then " \
310 #define CONFIG_AUTO_COMPLETE 1
312 * Miscellaneous configurable options
314 #define CONFIG_SYS_LONGHELP /* undef to save memory */
315 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
316 #define CONFIG_SYS_PROMPT "OMAP3 beagleboard.org # "
317 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
318 /* Print Buffer Size */
319 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
320 sizeof(CONFIG_SYS_PROMPT) + 16)
321 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
322 /* Boot Argument Buffer Size */
323 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
325 #define CONFIG_SYS_ALT_MEMTEST 1
326 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */
328 #define CONFIG_SYS_MEMTEST_END (0x87FFFFFF) /* 128MB */
329 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
331 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
335 * OMAP3 has 12 GP timers, they can be driven by the system clock
336 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
337 * This rate is divided by a local divisor.
339 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
340 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
341 #define CONFIG_SYS_HZ 1000
343 /*-----------------------------------------------------------------------
344 * Physical Memory Map
346 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
347 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
348 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
350 /*-----------------------------------------------------------------------
351 * FLASH and environment organization
354 /* **** PISMO SUPPORT *** */
356 /* Configure the PISMO */
357 #define PISMO1_NAND_SIZE GPMC_SIZE_128M
358 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M
360 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
362 #if defined(CONFIG_CMD_NAND)
363 #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
366 /* Monitor at start of flash */
367 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
368 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
370 #define CONFIG_ENV_IS_IN_NAND 1
371 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
372 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
374 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
375 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
376 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
378 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
379 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
380 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
381 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
382 CONFIG_SYS_INIT_RAM_SIZE - \
383 GENERATED_GBL_DATA_SIZE)
385 #define CONFIG_OMAP3_SPI
387 #define CONFIG_SYS_CACHELINE_SIZE 64
389 /* Defines for SPL */
391 #define CONFIG_SPL_FRAMEWORK
392 #define CONFIG_SPL_NAND_SIMPLE
393 #define CONFIG_SPL_TEXT_BASE 0x40200800
394 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
395 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
397 #define CONFIG_SPL_BSS_START_ADDR 0x80000000
398 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
400 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
401 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
402 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
403 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
405 #define CONFIG_SPL_BOARD_INIT
406 #define CONFIG_SPL_LIBCOMMON_SUPPORT
407 #define CONFIG_SPL_LIBDISK_SUPPORT
408 #define CONFIG_SPL_I2C_SUPPORT
409 #define CONFIG_SPL_LIBGENERIC_SUPPORT
410 #define CONFIG_SPL_MMC_SUPPORT
411 #define CONFIG_SPL_FAT_SUPPORT
412 #define CONFIG_SPL_SERIAL_SUPPORT
413 #define CONFIG_SPL_NAND_SUPPORT
414 #define CONFIG_SPL_NAND_BASE
415 #define CONFIG_SPL_NAND_DRIVERS
416 #define CONFIG_SPL_NAND_ECC
417 #define CONFIG_SPL_GPIO_SUPPORT
418 #define CONFIG_SPL_POWER_SUPPORT
419 #define CONFIG_SPL_OMAP3_ID_NAND
420 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
422 /* NAND boot config */
423 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
424 #define CONFIG_SYS_NAND_PAGE_COUNT 64
425 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
426 #define CONFIG_SYS_NAND_OOBSIZE 64
427 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
428 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
429 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
431 #define CONFIG_SYS_NAND_ECCSIZE 512
432 #define CONFIG_SYS_NAND_ECCBYTES 3
433 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
434 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
437 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
438 * 64 bytes before this address should be set aside for u-boot.img's
439 * header. That is 0x800FFFC0--0x80100000 should not be used for any
442 #define CONFIG_SYS_TEXT_BASE 0x80100000
443 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
444 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
446 #endif /* __CONFIG_H */