4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Kshitij Gupta <kshitij@ti.com>
7 * Configuration settings for the 242x TI H4 board.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * High Level Configuration Options
34 #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
35 #define CONFIG_OMAP 1 /* in a TI OMAP core */
36 #define CONFIG_OMAP2420 1 /* which is in a 2420 */
37 #define CONFIG_OMAP2420H4 1 /* and on a H4 board */
38 /*#define CONFIG_APTIX 1 #* define if on APTIX test chip */
39 /*#define CONFIG_VIRTIO 1 #* Using Virtio simulator */
41 /* Clock config to target*/
42 #define PRCM_CONFIG_II 1
43 /* #define PRCM_CONFIG_III 1 */
45 #include <asm/arch/omap2420.h> /* get chip and board defs */
47 /* On H4, NOR and NAND flash are mutual exclusive.
48 Define this if you want to use NAND
50 /*#define CONFIG_SYS_NAND_BOOT */
53 #define V_SCLK 1500000
55 #define V_SCLK 12000000
58 /* input clock of PLL */
59 /* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
60 #define CONFIG_SYS_CLK_FREQ V_SCLK
62 #undef CONFIG_USE_IRQ /* no support for IRQs */
63 #define CONFIG_MISC_INIT_R
65 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
66 #define CONFIG_SETUP_MEMORY_TAGS 1
67 #define CONFIG_INITRD_TAG 1
68 #define CONFIG_REVISION_TAG 1
71 * Size of malloc() pool
73 #define CONFIG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */
74 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
83 #define CONFIG_NET_MULTI
84 #define CONFIG_LAN91C96
85 #define CONFIG_LAN91C96_BASE (H4_CS1_BASE+0x300)
86 #define CONFIG_LAN91C96_EXT_PHY
89 * NS16550 Configuration
92 #define V_NS16550_CLK (6000000) /* 6MHz in current MaxSet */
94 #define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */
97 #define CONFIG_SYS_NS16550
98 #define CONFIG_SYS_NS16550_SERIAL
99 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
100 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */
101 #define CONFIG_SYS_NS16550_COM1 OMAP2420_UART1
104 * select serial console configuration
106 #define CONFIG_SERIAL1 1 /* UART1 on H4 */
111 #define CONFIG_HARD_I2C
112 #define CONFIG_SYS_I2C_SPEED 100000
113 #define CONFIG_SYS_I2C_SLAVE 1
114 #define CONFIG_DRIVER_OMAP24XX_I2C
116 /* allow to overwrite serial and ethaddr */
117 #define CONFIG_ENV_OVERWRITE
118 #define CONFIG_CONS_INDEX 1
119 #define CONFIG_BAUDRATE 115200
120 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
124 * Command line configuration.
126 #include <config_cmd_default.h>
128 #ifdef CONFIG_SYS_NAND_BOOT
129 #define CONFIG_CMD_DHCP
130 #define CONFIG_CMD_I2C
131 #define CONFIG_CMD_NAND
132 #define CONFIG_CMD_JFFS2
134 #define CONFIG_CMD_DHCP
135 #define CONFIG_CMD_I2C
136 #define CONFIG_CMD_JFFS2
138 #undef CONFIG_CMD_SOURCE
145 #define CONFIG_BOOTP_SUBNETMASK
146 #define CONFIG_BOOTP_GATEWAY
147 #define CONFIG_BOOTP_HOSTNAME
148 #define CONFIG_BOOTP_BOOTPATH
150 #define CONFIG_BOOTDELAY 3
152 #ifdef NFS_BOOT_DEFAULTS
153 #define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp"
155 #define CONFIG_BOOTARGS "root=/dev/ram0 rw mem=32M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
158 #define CONFIG_NETMASK 255.255.254.0
159 #define CONFIG_IPADDR 128.247.77.90
160 #define CONFIG_SERVERIP 128.247.77.158
161 #define CONFIG_BOOTFILE "uImage"
164 * Miscellaneous configurable options
166 #define CONFIG_SYS_LONGHELP /* undef to save memory */
168 # define CONFIG_SYS_PROMPT "OMAP2420 Aptix # "
170 # define CONFIG_SYS_PROMPT "OMAP242x H4 # "
172 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
173 /* Print Buffer Size */
174 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
175 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
176 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
178 #define CONFIG_SYS_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */
179 #define CONFIG_SYS_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M)
181 #define CONFIG_SYS_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */
183 /* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
184 * 32KHz clk, or from external sig. This rate is divided by a local divisor.
189 #define V_PTV 7 /* use with 12MHz/128 */
192 #define CONFIG_SYS_TIMERBASE OMAP2420_GPT2
193 #define CONFIG_SYS_PTV V_PTV /* 2^(PTV+1) */
194 #define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
196 /*-----------------------------------------------------------------------
199 * The stack sizes are set up in start.S using the settings below
201 #define CONFIG_STACKSIZE SZ_128K /* regular stack */
202 #ifdef CONFIG_USE_IRQ
203 #define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
204 #define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
207 /*-----------------------------------------------------------------------
208 * Physical Memory Map
210 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
211 #define PHYS_SDRAM_1 OMAP2420_SDRC_CS0
212 #define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
213 #define PHYS_SDRAM_2 OMAP2420_SDRC_CS1
215 #define PHYS_FLASH_SECT_SIZE SZ_128K
216 #define PHYS_FLASH_1 H4_CS0_BASE /* Flash Bank #1 */
217 #define PHYS_FLASH_SIZE_1 SZ_32M
218 #define PHYS_FLASH_2 (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */
219 #define PHYS_FLASH_SIZE_2 SZ_32M
221 /*-----------------------------------------------------------------------
222 * FLASH and environment organization
224 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
225 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
226 #define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
227 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
228 #define CONFIG_SYS_MONITOR_LEN SZ_128K /* Reserve 1 sector */
229 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE_1 }
231 #ifdef CONFIG_SYS_NAND_BOOT
232 #define CONFIG_ENV_IS_IN_NAND 1
233 #define CONFIG_ENV_OFFSET 0x80000 /* environment starts here */
235 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + SZ_128K)
236 #define CONFIG_ENV_IS_IN_FLASH 1
237 #define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
238 #define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */
241 /*-----------------------------------------------------------------------
242 * CFI FLASH driver setup
244 #define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
245 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
246 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
247 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
249 /* timeout values are in ticks */
250 #define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
251 #define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */
253 #define CONFIG_SYS_JFFS2_MEM_NAND
258 /* No command line, one static partition, whole device */
259 #undef CONFIG_CMD_MTDPARTS
260 #define CONFIG_JFFS2_DEV "nor1"
261 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
262 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
264 /* mtdparts command line support */
265 /* Note: fake mtd_id used, no linux mtd map file */
267 #define CONFIG_CMD_MTDPARTS
268 #define MTDIDS_DEFAULT "nor1=omap2420-1"
269 #define MTDPARTS_DEFAULT "mtdparts=omap2420-1:-(jffs2)"
272 #endif /* __CONFIG_H */