1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2019-2020
4 * Marvell <www.marvell.com>
7 #ifndef __OCTEON_COMMON_H__
8 #define __OCTEON_COMMON_H__
10 #if defined(CONFIG_RAM_OCTEON)
11 #define CONFIG_SYS_INIT_SP_OFFSET 0x20100000
13 /* No DDR init -> run in L2 cache with limited resources */
14 #define CONFIG_SYS_INIT_SP_OFFSET 0x00180000
17 #define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
19 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
21 #endif /* __OCTEON_COMMON_H__ */