1 /* SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2021 Linumiz
4 * Author: Navin Sankar Velliangiri <navin@linumiz.com>
10 #include <linux/sizes.h>
11 #include "mx6_common.h"
16 #define CONFIG_SYS_FSL_USDHC_NUM 1
19 #define CONFIG_MXC_UART_BASE UART1_BASE
22 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
24 #define CONFIG_NETMASK 255.255.255.0
26 /* Physical Memory Map */
27 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
29 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
30 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
31 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
33 #define CONFIG_SYS_INIT_SP_OFFSET \
34 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
35 #define CONFIG_SYS_INIT_SP_ADDR \
36 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
39 #define CONFIG_SYS_MAX_NAND_DEVICE 1
40 #define CONFIG_SYS_NAND_BASE 0x40000000
43 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
44 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
45 #define CONFIG_MXC_USB_FLAGS 0
46 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
49 #define IMX_FEC_BASE ENET_BASE_ADDR
50 #define CONFIG_FEC_MXC_PHYADDR 0x1
51 #define CONFIG_FEC_XCV_TYPE RMII
52 #define CONFIG_ETHPRIME "eth0"
55 #define CONFIG_FEC_ENET_DEV 1
57 #define CONFIG_EXTRA_ENV_SETTINGS \
58 "console=ttymxc0,115200n8\0" \
60 "fdtfile=imx6ull-seeed-npi-dev-board.dtb\0" \
61 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
62 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
63 "fdt_addr_r=0x82000000\0" \
64 "kernel_addr_r=0x81000000\0" \
65 "pxefile_addr_r=0x87100000\0" \
66 "ramdisk_addr_r=0x82100000\0" \
67 "scriptaddr=0x87000000\0" \
68 "root=/dev/mmcblk0p2 rootwait\0" \
71 #define BOOT_TARGET_DEVICES(func) \
73 func(UBIFS, ubifs, 0) \
77 #include <config_distro_bootcmd.h>
79 #endif /* _NPI_IMX6ULL_H */