2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 * Configuration settings for the Freescale i.MX7D SABRESD board.
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __MX7D_SABRESD_CONFIG_H
10 #define __MX7D_SABRESD_CONFIG_H
12 #include "mx7_common.h"
14 #define CONFIG_DBG_MONITOR
15 #define PHYS_SDRAM_SIZE SZ_1G
17 #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
19 /* Size of malloc() pool */
20 #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
23 #define CONFIG_FEC_MXC
25 #define CONFIG_FEC_XCV_TYPE RGMII
26 #define CONFIG_ETHPRIME "FEC"
27 #define CONFIG_FEC_MXC_PHYADDR 0
30 #define CONFIG_PHY_BROADCOM
32 #define IMX_FEC_BASE ENET_IPS_BASE_ADDR
35 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
37 #undef CONFIG_BOOTM_NETBSD
38 #undef CONFIG_BOOTM_PLAN9
39 #undef CONFIG_BOOTM_RTEMS
42 #define CONFIG_SYS_I2C_MXC
43 #define CONFIG_SYS_I2C_SPEED 100000
45 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
46 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
48 #ifdef CONFIG_IMX_BOOTAUX
49 /* Set to QSPI1 A flash at default */
50 #define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000
52 #define UPDATE_M4_ENV \
53 "m4image=m4_qspi.bin\0" \
54 "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
55 "update_m4_from_sd=" \
56 "if sf probe 0:0; then " \
57 "if run loadm4image; then " \
58 "setexpr fw_sz ${filesize} + 0xffff; " \
59 "setexpr fw_sz ${fw_sz} / 0x10000; " \
60 "setexpr fw_sz ${fw_sz} * 0x10000; " \
61 "sf erase 0x0 ${fw_sz}; " \
62 "sf write ${loadaddr} 0x0 ${filesize}; " \
65 "m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
67 #define UPDATE_M4_ENV ""
70 #define CONFIG_MFG_ENV_SETTINGS \
71 "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
73 "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
74 "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
75 "g_mass_storage.iSerialNumber=\"\" "\
78 "initrd_addr=0x83800000\0" \
79 "initrd_high=0xffffffff\0" \
80 "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
82 #define CONFIG_DFU_ENV_SETTINGS \
83 "dfu_alt_info=image raw 0 0x800000;"\
84 "u-boot raw 0 0x4000;"\
88 #define CONFIG_EXTRA_ENV_SETTINGS \
90 CONFIG_MFG_ENV_SETTINGS \
91 CONFIG_DFU_ENV_SETTINGS \
95 "fdt_high=0xffffffff\0" \
96 "initrd_high=0xffffffff\0" \
97 "fdt_file=imx7d-sdb.dtb\0" \
98 "fdt_addr=0x83000000\0" \
101 "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
102 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
103 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
104 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
105 "mmcautodetect=yes\0" \
106 "mmcargs=setenv bootargs console=${console},${baudrate} " \
107 "root=${mmcroot}\0" \
109 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
110 "bootscript=echo Running bootscript from mmc ...; " \
112 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
113 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
114 "mmcboot=echo Booting from mmc ...; " \
116 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
117 "if run loadfdt; then " \
118 "bootz ${loadaddr} - ${fdt_addr}; " \
120 "if test ${boot_fdt} = try; then " \
123 "echo WARN: Cannot load the DT; " \
129 "netargs=setenv bootargs console=${console},${baudrate} " \
131 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
132 "netboot=echo Booting from net ...; " \
134 "if test ${ip_dyn} = yes; then " \
135 "setenv get_cmd dhcp; " \
137 "setenv get_cmd tftp; " \
139 "${get_cmd} ${image}; " \
140 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
141 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
142 "bootz ${loadaddr} - ${fdt_addr}; " \
144 "if test ${boot_fdt} = try; then " \
147 "echo WARN: Cannot load the DT; " \
154 #define CONFIG_BOOTCOMMAND \
155 "mmc dev ${mmcdev};" \
156 "mmc dev ${mmcdev}; if mmc rescan; then " \
157 "if run loadbootscript; then " \
160 "if run loadimage; then " \
162 "else run netboot; " \
165 "else run netboot; fi"
167 #define CONFIG_SYS_MEMTEST_START 0x80000000
168 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
170 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
171 #define CONFIG_SYS_HZ 1000
173 /* Physical Memory Map */
174 #define CONFIG_NR_DRAM_BANKS 1
175 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
177 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
178 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
179 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
181 #define CONFIG_SYS_INIT_SP_OFFSET \
182 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
183 #define CONFIG_SYS_INIT_SP_ADDR \
184 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
186 /* environment organization */
187 #define CONFIG_ENV_SIZE SZ_8K
188 #define CONFIG_ENV_IS_IN_MMC
191 * If want to use nand, define CONFIG_NAND_MXS and rework board
192 * to support nand, since emmc has pin conflicts with nand
194 #ifdef CONFIG_NAND_MXS
195 #define CONFIG_CMD_NAND
196 #define CONFIG_CMD_NAND_TRIMFFS
199 #define CONFIG_SYS_MAX_NAND_DEVICE 1
200 #define CONFIG_SYS_NAND_BASE 0x40000000
201 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
202 #define CONFIG_SYS_NAND_ONFI_DETECTION
204 /* DMA stuff, needed for GPMI/MXS NAND support */
205 #define CONFIG_APBH_DMA
206 #define CONFIG_APBH_DMA_BURST
207 #define CONFIG_APBH_DMA_BURST8
210 #define CONFIG_ENV_OFFSET (12 * SZ_64K)
211 #ifdef CONFIG_NAND_MXS
212 #define CONFIG_SYS_FSL_USDHC_NUM 1
214 #define CONFIG_SYS_FSL_USDHC_NUM 2
217 #define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
218 #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
219 #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
222 #define CONFIG_USB_HOST_ETHER
223 #define CONFIG_USB_ETHER_ASIX
224 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
226 #define CONFIG_IMX_THERMAL
228 #define CONFIG_USBD_HS
230 #define CONFIG_USB_FUNCTION_MASS_STORAGE
233 #define CONFIG_VIDEO_MXS
234 #define CONFIG_VIDEO_LOGO
235 #define CONFIG_SPLASH_SCREEN
236 #define CONFIG_SPLASH_SCREEN_ALIGN
237 #define CONFIG_BMP_16BPP
238 #define CONFIG_VIDEO_BMP_RLE8
239 #define CONFIG_VIDEO_BMP_LOGO
242 #ifdef CONFIG_FSL_QSPI
243 #define CONFIG_SPI_FLASH
244 #define CONFIG_SPI_FLASH_MACRONIX
245 #define CONFIG_SPI_FLASH_BAR
246 #define CONFIG_SF_DEFAULT_BUS 0
247 #define CONFIG_SF_DEFAULT_CS 0
248 #define CONFIG_SF_DEFAULT_SPEED 40000000
249 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
250 #define FSL_QSPI_FLASH_NUM 1
251 #define FSL_QSPI_FLASH_SIZE SZ_64M
252 #define QSPI0_BASE_ADDR QSPI1_IPS_BASE_ADDR
253 #define QSPI0_AMBA_BASE QSPI0_ARB_BASE_ADDR
256 #endif /* __CONFIG_H */