2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 * Configuration settings for the Freescale i.MX7D SABRESD board.
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __MX7D_SABRESD_CONFIG_H
10 #define __MX7D_SABRESD_CONFIG_H
12 #include "mx7_common.h"
14 #define CONFIG_DBG_MONITOR
15 #define PHYS_SDRAM_SIZE SZ_1G
17 #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
19 /* Size of malloc() pool */
20 #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
23 #define CONFIG_FEC_MXC
25 #define CONFIG_FEC_XCV_TYPE RGMII
26 #define CONFIG_ETHPRIME "FEC"
27 #define CONFIG_FEC_MXC_PHYADDR 0
29 #define CONFIG_PHY_BROADCOM
31 #define IMX_FEC_BASE ENET_IPS_BASE_ADDR
34 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
36 #undef CONFIG_BOOTM_NETBSD
37 #undef CONFIG_BOOTM_PLAN9
38 #undef CONFIG_BOOTM_RTEMS
41 #define CONFIG_SYS_I2C_MXC
42 #define CONFIG_SYS_I2C_SPEED 100000
44 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
45 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
47 #ifdef CONFIG_IMX_BOOTAUX
48 /* Set to QSPI1 A flash at default */
49 #define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000
51 #define UPDATE_M4_ENV \
52 "m4image=m4_qspi.bin\0" \
53 "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
54 "update_m4_from_sd=" \
55 "if sf probe 0:0; then " \
56 "if run loadm4image; then " \
57 "setexpr fw_sz ${filesize} + 0xffff; " \
58 "setexpr fw_sz ${fw_sz} / 0x10000; " \
59 "setexpr fw_sz ${fw_sz} * 0x10000; " \
60 "sf erase 0x0 ${fw_sz}; " \
61 "sf write ${loadaddr} 0x0 ${filesize}; " \
64 "m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
66 #define UPDATE_M4_ENV ""
69 #define CONFIG_MFG_ENV_SETTINGS \
70 "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
72 "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
73 "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
74 "g_mass_storage.iSerialNumber=\"\" "\
77 "initrd_addr=0x83800000\0" \
78 "initrd_high=0xffffffff\0" \
79 "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
81 #define CONFIG_DFU_ENV_SETTINGS \
82 "dfu_alt_info=image raw 0 0x800000;"\
83 "u-boot raw 0 0x4000;"\
87 #define CONFIG_EXTRA_ENV_SETTINGS \
89 CONFIG_MFG_ENV_SETTINGS \
90 CONFIG_DFU_ENV_SETTINGS \
94 "fdt_high=0xffffffff\0" \
95 "initrd_high=0xffffffff\0" \
96 "fdt_file=imx7d-sdb.dtb\0" \
97 "fdt_addr=0x83000000\0" \
100 "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
101 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
102 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
103 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
104 "mmcautodetect=yes\0" \
105 "mmcargs=setenv bootargs console=${console},${baudrate} " \
106 "root=${mmcroot}\0" \
108 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
109 "bootscript=echo Running bootscript from mmc ...; " \
111 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
112 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
113 "mmcboot=echo Booting from mmc ...; " \
115 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
116 "if run loadfdt; then " \
117 "bootz ${loadaddr} - ${fdt_addr}; " \
119 "if test ${boot_fdt} = try; then " \
122 "echo WARN: Cannot load the DT; " \
128 "netargs=setenv bootargs console=${console},${baudrate} " \
130 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
131 "netboot=echo Booting from net ...; " \
133 "if test ${ip_dyn} = yes; then " \
134 "setenv get_cmd dhcp; " \
136 "setenv get_cmd tftp; " \
138 "${get_cmd} ${image}; " \
139 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
140 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
141 "bootz ${loadaddr} - ${fdt_addr}; " \
143 "if test ${boot_fdt} = try; then " \
146 "echo WARN: Cannot load the DT; " \
153 #define CONFIG_BOOTCOMMAND \
154 "mmc dev ${mmcdev};" \
155 "mmc dev ${mmcdev}; if mmc rescan; then " \
156 "if run loadbootscript; then " \
159 "if run loadimage; then " \
161 "else run netboot; " \
164 "else run netboot; fi"
166 #define CONFIG_SYS_MEMTEST_START 0x80000000
167 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
169 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
170 #define CONFIG_SYS_HZ 1000
172 /* Physical Memory Map */
173 #define CONFIG_NR_DRAM_BANKS 1
174 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
176 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
177 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
178 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
180 #define CONFIG_SYS_INIT_SP_OFFSET \
181 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
182 #define CONFIG_SYS_INIT_SP_ADDR \
183 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
185 /* environment organization */
186 #define CONFIG_ENV_SIZE SZ_8K
189 * If want to use nand, define CONFIG_NAND_MXS and rework board
190 * to support nand, since emmc has pin conflicts with nand
192 #ifdef CONFIG_NAND_MXS
194 #define CONFIG_SYS_MAX_NAND_DEVICE 1
195 #define CONFIG_SYS_NAND_BASE 0x40000000
196 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
197 #define CONFIG_SYS_NAND_ONFI_DETECTION
199 /* DMA stuff, needed for GPMI/MXS NAND support */
202 #define CONFIG_ENV_OFFSET (12 * SZ_64K)
203 #ifdef CONFIG_NAND_MXS
204 #define CONFIG_SYS_FSL_USDHC_NUM 1
206 #define CONFIG_SYS_FSL_USDHC_NUM 2
209 #define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
210 #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
211 #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
214 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
216 #define CONFIG_IMX_THERMAL
218 #define CONFIG_USBD_HS
221 #define CONFIG_VIDEO_MXS
222 #define CONFIG_VIDEO_LOGO
223 #define CONFIG_SPLASH_SCREEN
224 #define CONFIG_SPLASH_SCREEN_ALIGN
225 #define CONFIG_BMP_16BPP
226 #define CONFIG_VIDEO_BMP_RLE8
227 #define CONFIG_VIDEO_BMP_LOGO
230 #ifdef CONFIG_FSL_QSPI
231 #define CONFIG_SPI_FLASH
232 #define CONFIG_SPI_FLASH_MACRONIX
233 #define CONFIG_SPI_FLASH_BAR
234 #define CONFIG_SF_DEFAULT_BUS 0
235 #define CONFIG_SF_DEFAULT_CS 0
236 #define CONFIG_SF_DEFAULT_SPEED 40000000
237 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
238 #define FSL_QSPI_FLASH_NUM 1
239 #define FSL_QSPI_FLASH_SIZE SZ_64M
240 #define QSPI0_BASE_ADDR QSPI1_IPS_BASE_ADDR
241 #define QSPI0_AMBA_BASE QSPI0_ARB_BASE_ADDR
244 #endif /* __CONFIG_H */