1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015 Freescale Semiconductor, Inc.
5 * Configuration settings for the Freescale i.MX7D SABRESD board.
8 #ifndef __MX7D_SABRESD_CONFIG_H
9 #define __MX7D_SABRESD_CONFIG_H
11 #include "mx7_common.h"
13 #define CONFIG_DBG_MONITOR
14 #define PHYS_SDRAM_SIZE SZ_1G
16 #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
18 /* Size of malloc() pool */
19 #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
22 #define CONFIG_FEC_MXC
24 #define CONFIG_FEC_XCV_TYPE RGMII
25 #define CONFIG_ETHPRIME "FEC"
26 #define CONFIG_FEC_MXC_PHYADDR 0
28 #define CONFIG_PHY_BROADCOM
30 #define IMX_FEC_BASE ENET_IPS_BASE_ADDR
33 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
35 #undef CONFIG_BOOTM_NETBSD
36 #undef CONFIG_BOOTM_PLAN9
37 #undef CONFIG_BOOTM_RTEMS
40 #define CONFIG_SYS_I2C_MXC
41 #define CONFIG_SYS_I2C_SPEED 100000
43 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
44 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
46 #ifdef CONFIG_IMX_BOOTAUX
47 /* Set to QSPI1 A flash at default */
48 #define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000
50 #define UPDATE_M4_ENV \
51 "m4image=m4_qspi.bin\0" \
52 "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
53 "update_m4_from_sd=" \
54 "if sf probe 0:0; then " \
55 "if run loadm4image; then " \
56 "setexpr fw_sz ${filesize} + 0xffff; " \
57 "setexpr fw_sz ${fw_sz} / 0x10000; " \
58 "setexpr fw_sz ${fw_sz} * 0x10000; " \
59 "sf erase 0x0 ${fw_sz}; " \
60 "sf write ${loadaddr} 0x0 ${filesize}; " \
63 "m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
65 #define UPDATE_M4_ENV ""
68 #define CONFIG_MFG_ENV_SETTINGS \
69 "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
71 "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
72 "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
73 "g_mass_storage.iSerialNumber=\"\" "\
76 "initrd_addr=0x83800000\0" \
77 "initrd_high=0xffffffff\0" \
78 "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
80 #define CONFIG_DFU_ENV_SETTINGS \
81 "dfu_alt_info=image raw 0 0x800000;"\
82 "u-boot raw 0 0x4000;"\
86 #define CONFIG_EXTRA_ENV_SETTINGS \
88 CONFIG_MFG_ENV_SETTINGS \
89 CONFIG_DFU_ENV_SETTINGS \
93 "fdt_high=0xffffffff\0" \
94 "initrd_high=0xffffffff\0" \
95 "fdt_file=imx7d-sdb.dtb\0" \
96 "fdt_addr=0x83000000\0" \
99 "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
100 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
101 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
102 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
103 "mmcautodetect=yes\0" \
104 "mmcargs=setenv bootargs console=${console},${baudrate} " \
105 "root=${mmcroot}\0" \
107 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
108 "bootscript=echo Running bootscript from mmc ...; " \
110 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
111 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
112 "mmcboot=echo Booting from mmc ...; " \
114 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
115 "if run loadfdt; then " \
116 "bootz ${loadaddr} - ${fdt_addr}; " \
118 "if test ${boot_fdt} = try; then " \
121 "echo WARN: Cannot load the DT; " \
127 "netargs=setenv bootargs console=${console},${baudrate} " \
129 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
130 "netboot=echo Booting from net ...; " \
132 "if test ${ip_dyn} = yes; then " \
133 "setenv get_cmd dhcp; " \
135 "setenv get_cmd tftp; " \
137 "${get_cmd} ${image}; " \
138 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
139 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
140 "bootz ${loadaddr} - ${fdt_addr}; " \
142 "if test ${boot_fdt} = try; then " \
145 "echo WARN: Cannot load the DT; " \
152 #define CONFIG_BOOTCOMMAND \
153 "mmc dev ${mmcdev};" \
154 "mmc dev ${mmcdev}; if mmc rescan; then " \
155 "if run loadbootscript; then " \
158 "if run loadimage; then " \
160 "else run netboot; " \
163 "else run netboot; fi"
165 #define CONFIG_SYS_MEMTEST_START 0x80000000
166 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
168 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
169 #define CONFIG_SYS_HZ 1000
171 /* Physical Memory Map */
172 #define CONFIG_NR_DRAM_BANKS 1
173 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
175 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
176 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
177 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
179 #define CONFIG_SYS_INIT_SP_OFFSET \
180 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
181 #define CONFIG_SYS_INIT_SP_ADDR \
182 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
184 /* environment organization */
185 #define CONFIG_ENV_SIZE SZ_8K
188 * If want to use nand, define CONFIG_NAND_MXS and rework board
189 * to support nand, since emmc has pin conflicts with nand
191 #ifdef CONFIG_NAND_MXS
193 #define CONFIG_SYS_MAX_NAND_DEVICE 1
194 #define CONFIG_SYS_NAND_BASE 0x40000000
195 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
196 #define CONFIG_SYS_NAND_ONFI_DETECTION
198 /* DMA stuff, needed for GPMI/MXS NAND support */
201 #define CONFIG_ENV_OFFSET (12 * SZ_64K)
202 #ifdef CONFIG_NAND_MXS
203 #define CONFIG_SYS_FSL_USDHC_NUM 1
205 #define CONFIG_SYS_FSL_USDHC_NUM 2
208 #define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
209 #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
210 #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
213 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
215 #define CONFIG_IMX_THERMAL
217 #define CONFIG_USBD_HS
220 #define CONFIG_VIDEO_MXS
221 #define CONFIG_VIDEO_LOGO
222 #define CONFIG_SPLASH_SCREEN
223 #define CONFIG_SPLASH_SCREEN_ALIGN
224 #define CONFIG_BMP_16BPP
225 #define CONFIG_VIDEO_BMP_RLE8
226 #define CONFIG_VIDEO_BMP_LOGO
229 #ifdef CONFIG_FSL_QSPI
230 #define CONFIG_SPI_FLASH
231 #define CONFIG_SPI_FLASH_MACRONIX
232 #define CONFIG_SPI_FLASH_BAR
233 #define CONFIG_SF_DEFAULT_BUS 0
234 #define CONFIG_SF_DEFAULT_CS 0
235 #define CONFIG_SF_DEFAULT_SPEED 40000000
236 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
237 #define FSL_QSPI_FLASH_NUM 1
238 #define FSL_QSPI_FLASH_SIZE SZ_64M
239 #define QSPI0_BASE_ADDR QSPI1_IPS_BASE_ADDR
240 #define QSPI0_AMBA_BASE QSPI0_ARB_BASE_ADDR
243 #endif /* __CONFIG_H */