2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 * Configuration settings for the Freescale i.MX6UL 14x14 EVK board.
6 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef __MX6UL_14X14_EVK_CONFIG_H
9 #define __MX6UL_14X14_EVK_CONFIG_H
11 #include <asm/arch/imx-regs.h>
12 #include <linux/sizes.h>
13 #include "mx6_common.h"
14 #include <asm/imx-common/gpio.h>
16 #define is_mx6ul_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK)
21 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
23 /* Size of malloc() pool */
24 #define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
26 #define CONFIG_BOARD_EARLY_INIT_F
27 #define CONFIG_BOARD_LATE_INIT
29 #define CONFIG_MXC_UART
30 #define CONFIG_MXC_UART_BASE UART1_BASE
33 #ifdef CONFIG_FSL_USDHC
34 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
36 /* NAND pin conflicts with usdhc2 */
37 #ifdef CONFIG_NAND_MXS
38 #define CONFIG_SYS_FSL_USDHC_NUM 1
40 #define CONFIG_SYS_FSL_USDHC_NUM 2
47 #define CONFIG_SYS_I2C
48 #define CONFIG_SYS_I2C_MXC
49 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
50 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
51 #define CONFIG_SYS_I2C_SPEED 100000
53 /* PMIC only for 9X9 EVK */
55 #define CONFIG_POWER_I2C
56 #define CONFIG_POWER_PFUZE3000
57 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
60 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
62 #define CONFIG_EXTRA_ENV_SETTINGS \
66 "fdt_high=0xffffffff\0" \
67 "initrd_high=0xffffffff\0" \
68 "fdt_file=undefined\0" \
69 "fdt_addr=0x83000000\0" \
72 "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
73 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
74 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
75 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
76 "mmcautodetect=yes\0" \
77 "mmcargs=setenv bootargs console=${console},${baudrate} " \
80 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
81 "bootscript=echo Running bootscript from mmc ...; " \
83 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
84 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
85 "mmcboot=echo Booting from mmc ...; " \
87 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
88 "if run loadfdt; then " \
89 "bootz ${loadaddr} - ${fdt_addr}; " \
91 "if test ${boot_fdt} = try; then " \
94 "echo WARN: Cannot load the DT; " \
100 "netargs=setenv bootargs console=${console},${baudrate} " \
102 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
103 "netboot=echo Booting from net ...; " \
105 "if test ${ip_dyn} = yes; then " \
106 "setenv get_cmd dhcp; " \
108 "setenv get_cmd tftp; " \
110 "${get_cmd} ${image}; " \
111 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
112 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
113 "bootz ${loadaddr} - ${fdt_addr}; " \
115 "if test ${boot_fdt} = try; then " \
118 "echo WARN: Cannot load the DT; " \
125 "if test $fdt_file = undefined; then " \
126 "if test $board_name = EVK && test $board_rev = 9X9; then " \
127 "setenv fdt_file imx6ul-9x9-evk.dtb; fi; " \
128 "if test $board_name = EVK && test $board_rev = 14X14; then " \
129 "setenv fdt_file imx6ul-14x14-evk.dtb; fi; " \
130 "if test $fdt_file = undefined; then " \
131 "echo WARNING: Could not determine dtb to use; fi; " \
134 #define CONFIG_BOOTCOMMAND \
136 "mmc dev ${mmcdev};" \
137 "mmc dev ${mmcdev}; if mmc rescan; then " \
138 "if run loadbootscript; then " \
141 "if run loadimage; then " \
143 "else run netboot; " \
146 "else run netboot; fi"
148 /* Miscellaneous configurable options */
149 #define CONFIG_SYS_MEMTEST_START 0x80000000
150 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
152 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
153 #define CONFIG_SYS_HZ 1000
155 #define CONFIG_CMDLINE_EDITING
156 #define CONFIG_STACKSIZE SZ_128K
158 /* Physical Memory Map */
159 #define CONFIG_NR_DRAM_BANKS 1
160 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
162 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
163 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
164 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
166 #define CONFIG_SYS_INIT_SP_OFFSET \
167 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
168 #define CONFIG_SYS_INIT_SP_ADDR \
169 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
171 /* FLASH and environment organization */
172 #define CONFIG_SYS_NO_FLASH
174 #define CONFIG_ENV_SIZE SZ_8K
175 #define CONFIG_ENV_IS_IN_MMC
176 #define CONFIG_ENV_OFFSET (8 * SZ_64K)
177 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
178 #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
179 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
181 #define CONFIG_CMD_BMODE
183 #ifndef CONFIG_SYS_DCACHE_OFF
186 #ifdef CONFIG_FSL_QSPI
187 #define CONFIG_SF_DEFAULT_BUS 0
188 #define CONFIG_SF_DEFAULT_CS 0
189 #define CONFIG_SF_DEFAULT_SPEED 40000000
190 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
191 #define FSL_QSPI_FLASH_NUM 1
192 #define FSL_QSPI_FLASH_SIZE SZ_32M
196 #ifdef CONFIG_CMD_USB
197 #define CONFIG_USB_EHCI
198 #define CONFIG_USB_EHCI_MX6
199 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
200 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
201 #define CONFIG_MXC_USB_FLAGS 0
202 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
205 #ifdef CONFIG_CMD_NET
206 #define CONFIG_FEC_MXC
208 #define CONFIG_FEC_ENET_DEV 1
210 #if (CONFIG_FEC_ENET_DEV == 0)
211 #define IMX_FEC_BASE ENET_BASE_ADDR
212 #define CONFIG_FEC_MXC_PHYADDR 0x2
213 #define CONFIG_FEC_XCV_TYPE RMII
214 #elif (CONFIG_FEC_ENET_DEV == 1)
215 #define IMX_FEC_BASE ENET2_BASE_ADDR
216 #define CONFIG_FEC_MXC_PHYADDR 0x1
217 #define CONFIG_FEC_XCV_TYPE RMII
219 #define CONFIG_ETHPRIME "FEC"
221 #define CONFIG_PHYLIB
222 #define CONFIG_PHY_MICREL
225 #define CONFIG_IMX_THERMAL
227 #ifndef CONFIG_SPL_BUILD
230 #define CONFIG_CFB_CONSOLE
231 #define CONFIG_VIDEO_MXS
232 #define CONFIG_VIDEO_LOGO
233 #define CONFIG_VIDEO_SW_CURSOR
234 #define CONFIG_VGA_AS_SINGLE_DEVICE
235 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
236 #define CONFIG_SPLASH_SCREEN
237 #define CONFIG_SPLASH_SCREEN_ALIGN
238 #define CONFIG_CMD_BMP
239 #define CONFIG_BMP_16BPP
240 #define CONFIG_VIDEO_BMP_RLE8
241 #define CONFIG_VIDEO_BMP_LOGO
242 #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR