2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 * Configuration settings for the Freescale i.MX6UL 14x14 EVK board.
6 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef __MX6UL_14X14_EVK_CONFIG_H
9 #define __MX6UL_14X14_EVK_CONFIG_H
12 #include <asm/arch/imx-regs.h>
13 #include <linux/sizes.h>
14 #include "mx6_common.h"
15 #include <asm/imx-common/gpio.h>
17 #define is_mx6ul_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK)
20 #define CONFIG_SPL_LIBCOMMON_SUPPORT
21 #define CONFIG_SPL_MMC_SUPPORT
22 #define CONFIG_SPL_FAT_SUPPORT
25 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
27 #define CONFIG_ROM_UNIFIED_SECTIONS
28 #define CONFIG_SYS_GENERIC_BOARD
29 #define CONFIG_DISPLAY_CPUINFO
30 #define CONFIG_DISPLAY_BOARDINFO
32 /* Size of malloc() pool */
33 #define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
35 #define CONFIG_BOARD_EARLY_INIT_F
36 #define CONFIG_BOARD_LATE_INIT
38 #define CONFIG_MXC_UART
39 #define CONFIG_MXC_UART_BASE UART1_BASE
42 #ifdef CONFIG_FSL_USDHC
43 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
45 /* NAND pin conflicts with usdhc2 */
46 #ifdef CONFIG_NAND_MXS
47 #define CONFIG_SYS_FSL_USDHC_NUM 1
49 #define CONFIG_SYS_FSL_USDHC_NUM 2
52 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
55 #undef CONFIG_BOOTM_NETBSD
56 #undef CONFIG_BOOTM_PLAN9
57 #undef CONFIG_BOOTM_RTEMS
59 #undef CONFIG_CMD_EXPORTENV
60 #undef CONFIG_CMD_IMPORTENV
63 #define CONFIG_CMD_I2C
65 #define CONFIG_SYS_I2C
66 #define CONFIG_SYS_I2C_MXC
67 #define CONFIG_SYS_I2C_SPEED 100000
69 /* PMIC only for 9X9 EVK */
71 #define CONFIG_POWER_I2C
72 #define CONFIG_POWER_PFUZE3000
73 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
76 #undef CONFIG_CMD_IMLS
78 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
80 #define CONFIG_EXTRA_ENV_SETTINGS \
84 "fdt_high=0xffffffff\0" \
85 "initrd_high=0xffffffff\0" \
86 "fdt_file=undefined\0" \
87 "fdt_addr=0x83000000\0" \
90 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
91 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
92 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
93 "mmcautodetect=yes\0" \
94 "mmcargs=setenv bootargs console=${console},${baudrate} " \
97 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
98 "bootscript=echo Running bootscript from mmc ...; " \
100 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
101 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
102 "mmcboot=echo Booting from mmc ...; " \
104 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
105 "if run loadfdt; then " \
106 "bootz ${loadaddr} - ${fdt_addr}; " \
108 "if test ${boot_fdt} = try; then " \
111 "echo WARN: Cannot load the DT; " \
117 "netargs=setenv bootargs console=${console},${baudrate} " \
119 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
120 "netboot=echo Booting from net ...; " \
122 "if test ${ip_dyn} = yes; then " \
123 "setenv get_cmd dhcp; " \
125 "setenv get_cmd tftp; " \
127 "${get_cmd} ${image}; " \
128 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
129 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
130 "bootz ${loadaddr} - ${fdt_addr}; " \
132 "if test ${boot_fdt} = try; then " \
135 "echo WARN: Cannot load the DT; " \
142 "if test $fdt_file = undefined; then " \
143 "if test $board_name = EVK && test $board_rev = 9X9; then " \
144 "setenv fdt_file imx6ul-9x9-evk.dtb; fi; " \
145 "if test $board_name = EVK && test $board_rev = 14X14; then " \
146 "setenv fdt_file imx6ul-14x14-evk.dtb; fi; " \
147 "if test $fdt_file = undefined; then " \
148 "echo WARNING: Could not determine dtb to use; fi; " \
151 #define CONFIG_BOOTCOMMAND \
153 "mmc dev ${mmcdev};" \
154 "mmc dev ${mmcdev}; if mmc rescan; then " \
155 "if run loadbootscript; then " \
158 "if run loadimage; then " \
160 "else run netboot; " \
163 "else run netboot; fi"
165 /* Miscellaneous configurable options */
166 /* Print Buffer Size */
167 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
169 #define CONFIG_CMD_MEMTEST
170 #define CONFIG_SYS_MEMTEST_START 0x80000000
171 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000)
173 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
174 #define CONFIG_SYS_HZ 1000
176 #define CONFIG_CMDLINE_EDITING
177 #define CONFIG_STACKSIZE SZ_128K
179 /* Physical Memory Map */
180 #define CONFIG_NR_DRAM_BANKS 1
181 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
183 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
184 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
185 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
187 #define CONFIG_SYS_INIT_SP_OFFSET \
188 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
189 #define CONFIG_SYS_INIT_SP_ADDR \
190 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
192 /* FLASH and environment organization */
193 #define CONFIG_SYS_NO_FLASH
195 #define CONFIG_ENV_SIZE SZ_8K
196 #define CONFIG_ENV_IS_IN_MMC
197 #define CONFIG_ENV_OFFSET (8 * SZ_64K)
198 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
199 #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
200 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
202 #define CONFIG_OF_LIBFDT
203 #define CONFIG_CMD_BOOTZ
204 #define CONFIG_CMD_BMODE
206 #ifndef CONFIG_SYS_DCACHE_OFF
207 #define CONFIG_CMD_CACHE
210 #define CONFIG_FSL_QSPI
211 #ifdef CONFIG_FSL_QSPI
212 #define CONFIG_CMD_SF
213 #define CONFIG_SPI_FLASH
214 #define CONFIG_SPI_FLASH_STMICRO
215 #define CONFIG_SPI_FLASH_BAR
216 #define CONFIG_SF_DEFAULT_BUS 0
217 #define CONFIG_SF_DEFAULT_CS 0
218 #define CONFIG_SF_DEFAULT_SPEED 40000000
219 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
220 #define FSL_QSPI_FLASH_NUM 1
221 #define FSL_QSPI_FLASH_SIZE SZ_32M
225 #define CONFIG_CMD_USB
226 #ifdef CONFIG_CMD_USB
227 #define CONFIG_USB_EHCI
228 #define CONFIG_USB_EHCI_MX6
229 #define CONFIG_USB_STORAGE
230 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
231 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
232 #define CONFIG_MXC_USB_FLAGS 0
233 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
236 #ifdef CONFIG_CMD_NET
237 #define CONFIG_FEC_MXC
239 #define CONFIG_FEC_ENET_DEV 1
241 #if (CONFIG_FEC_ENET_DEV == 0)
242 #define IMX_FEC_BASE ENET_BASE_ADDR
243 #define CONFIG_FEC_MXC_PHYADDR 0x2
244 #define CONFIG_FEC_XCV_TYPE RMII
245 #elif (CONFIG_FEC_ENET_DEV == 1)
246 #define IMX_FEC_BASE ENET2_BASE_ADDR
247 #define CONFIG_FEC_MXC_PHYADDR 0x1
248 #define CONFIG_FEC_XCV_TYPE RMII
250 #define CONFIG_ETHPRIME "FEC"
252 #define CONFIG_PHYLIB
253 #define CONFIG_PHY_MICREL
254 #define CONFIG_FEC_DMA_MINALIGN 64
257 #define CONFIG_IMX_THERMAL